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FDC37CXFR 参数 Datasheet PDF下载

FDC37CXFR图片预览
型号: FDC37CXFR
PDF下载: 下载PDF文件 查看货源
内容描述: 即插即用兼容超I / O控制器,提供快速IR [Plug and Play Compatible Ultra I/O Controller with Fast IR]
分类和应用: 控制器
文件页数/大小: 258 页 / 898 K
品牌: SMSC [ SMSC CORPORATION ]
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The INDEX PORT is used to select  
a
Chip - Level (Global) Control/Configuration  
Registers[0x00-0x2F]  
configuration register in the chip. The DATA  
PORT is then used to access the selected  
register. These registers are accessable only in  
the Configuration Mode.  
The chip-level (global) registers lie in the  
address range [0x00-0x2F]. The design MUST  
use all 8 bits of the ADDRESS Port for register  
selection. All unimplemented registers and bits  
ignore writes and return zero when read.  
Table 76 - Chip - Level Registers  
ADDRESS DESCRIPTION  
REGISTER  
STATE  
Chip (Global) Control Registers  
0x00 -  
0x01  
Reserved - Writes are ignored, reads return 0.  
Config Control  
0x02 W  
The hardware automatically clears this bit after the  
write; there is no need for software to clear the bits.  
Bit 0  
C
Default = 0x00  
on Vcc POR or  
Reset_Drv  
= 1: Soft Reset. Refer to the "Configuration  
Registers" table for the soft reset value for each  
register.  
Index Address  
0x03 R/W Bit[7]  
= 1 Enable GP1, GP2, WDT_CTRL, GP4, GP5,  
GP6, GP7, Soft Power and SMI Enable and  
Status Register access when not in  
configuration mode  
Default = 0x03  
on Vcc POR or  
Reset_Drv  
= 0 Disable GP1, GP2, WDT_CTRL, GP4, GP5,  
GP6, GP7, Soft Power and SMI Enable and  
Status Register access when not in  
configuration mode (Default)  
Bits [6:2]  
Reserved - Writes are ignored, reads return 0.  
Bits[1:0]  
Sets GP1/GP2 selection register used when in Run  
mode (not in Configuration Mode).  
= 11  
= 10  
= 01  
= 00  
0xEA (Default)  
0xE4  
0xE2  
0xE0  
0x04 - 0x06  
Reserved - Writes are ignored, reads return 0.  
177  
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