Writing to the DMA Mode Select bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are
not available on this chip.
Reserved, Bits 4 - 5
Bits 4 to 5 are RESERVED. Reserved bits cannot be written and return 0 when read.
RCVR Trigger, Bits 6 - 7
The RCVR Trigger bits are used to set the trigger level for the RCVR FIFO interrupt (Table 53).
Table 53 - RCVR Trigger Encoding
RCVR
RCVR FIFO Trigger Level
(BYTES)
TRIGGER
Bit 7
Bit 6
0
0
1
4
0
1
1
1
0
1
8
14
LINE CONTROL REGISTER (LCR)
The Line Control register (Address Offset = 3H, DLAB = 0, READ/WRITE) contains the formatting information for the
serial line.
Word Length Select, Bits 0 - 1
The Word Length Select bits specify the number of bits in each transmitted or received serial character. Note: the
Start, Stop and Parity bits are not included in the word length. The encoding of the Word Length bits is shown in
Table 54.
Table 54 - Word Length Encoding
WORD LENGTH
SELECT
WORD LENGTH (Bits)
Bit 1
Bit 0
0
0
1
1
0
1
0
1
5
6
7
8
SMSC DS – FDC37N769
Page 63 of 137
Rev. 12/21/2000
SMSC [ SMSC CORPORATION ]
