ETHREI, Bit 1
The ETHREI bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”.
ELSI, Bit 2
The ELSI bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the interrupt
are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source.
EMSI, Bit 3
The EMSI bit enables the MODEM Status Interrupt when set to logic “1”. An MSI is caused when one of the Modem
Status Register bits changes state.
Reserved, Bits 4 - 7
Bits 4 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read.
INTERRUPT IDENTIFICATION REGISTER (IIR)
By accessing the Interrupt Identification register (Address Offset = 2H, DLAB = X, READ), the host CPU can
determine the highest priority interrupt and its source. Four levels of interrupt priority exist. They are in descending
order of priority:
1. Receiver Line Status (highest priority)
2. Received Data Ready
3. Transmitter Holding Register Empty
4. MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt
Identification Register (refer to the Interrupt Control Table, Table 52). When the CPU accesses the IIR, the Serial
Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access,
even if the Serial Port records new interrupts, the current indication does not change until access is completed.
Interrupt Pending, Bit 0
The Interrupt Pending bit can be used in either a hardwired prioritized or polled environment to indicate whether an
interrupt is pending. When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a
pointer to the appropriate internal service routine. When bit 0 is a logic “1”, no interrupt is pending.
Interrupt ID, Bits 1 - 2
The Interrupt ID bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt
Control Table (Table 52).
Time-Out, Bit 3
In non-FIFO mode, the Time-Out bit is a logic “0”. In FIFO mode the Time-Out bit is set along with bit 2 when a time-
out interrupt is pending.
Reserved, Bits 4 - 5
Bits 4 to 5 are RESERVED. Reserved bits cannot be written and return 0 when read.
FIFOs Enabled, Bits 6 - 7
The FIFOs Enabled bits are set when the FIFO CONTROL Register bit 0 equals 1.
Table 52 - Interrupt Control
FIFO
MODE
ONLY
BIT
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
BIT
2
BIT
1
BIT
0
PRIORITY
INTERRUPT
TYPE
INTERRUPT
SOURCE
None
INTERRUPT
3
LEVEL
RESET CONTROL
0
0
0
1
-
None
-
SMSC DS – FDC37N769
Page 61 of 137
Rev. 12/21/2000
SMSC [ SMSC CORPORATION ]
