MODEM STATUS REGISTER (MSR)
The Modem Status register (Address Offset = 6H, DLAB = X, READ/WRITE) provides the current state of the control
lines from the MODEM or peripheral device. In addition to this current state information, four bits of the MODEM
Status Register provide state change information. These four bits are set to logic “1” whenever a control input
from the MODEM changes state. They are reset to logic “0” whenever the MODEM Status Register is read.
Delta Clear To Send, Bit 0
The Delta Clear To Send (DCTS) bit indicates that the nCTS input to the chip has changed state since the last
time the MSR was read.
Delta Data Set Ready, Bit 1
The Delta Data Set Ready (DDSR) bit indicates that the nDSR input has changed state since the last time the MSR
was read.
Trailing Edge Of Ring Indicator, Bit 2
The Trailing Edge of Ring Indicator (TERI) bit indicates that the nRI input has changed from logic “0” to logic “1”.
Delta Data Carrier Detect, Bit 3
The Delta Data Carrier Detect (DDCD) bit indicates that the nDCD input to the chip has changed state.
Note: Whenever bits 0, 1, 2, or 3 are set to a logic “1”, a MODEM Status Interrupt is generated.
Clear To Send, Bit 4
The Clear To Send bit is the complement of the Clear To Send input (nCTS). If the Loop bit of the MCR is set to logic
“1”, this bit is equivalent to nRTS in the MCR.
Data Set Ready, Bit 5
The Data Set Ready bit is the complement of the Data Set Ready input (nDSR). If the Loop bit of the MCR is set to
logic “1”, this bit is equivalent to DTR in the MCR.
Ring Indicator, Bit 6
The Ring Indicator bit is the complement of the Ring Indicator input (nRI). If the Loop bit of the MCR is set to logic
“1”, this bit is equivalent to OUT1 in the MCR.
Data Carrier Detect, Bit 7
The Data Carrier Detect bit is the complement of the Data Carrier Detect input (nDCD). If the Loop bit of the MCR is
set to logic “1”, this bit is equivalent to OUT2 in the MCR.
SCRATCHPAD REGISTER (SCR)
The Scratchpad register (Address Offset =7H, DLAB =X, READ/WRITE) has no effect on the operation of the Serial
Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily.
PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES
The internal Baud Rate Generator (BRG) using the Programmable Baud Rate Generator Divisor Latches DDL and
DDM (Address Offset = 0 and 1, DLAB = 1, READ/WRITE) is capable of taking any clock input (DC to 3 MHz) and
dividing it by any divisor from 1 to 65535. The Baud Rate Generator output is 16x the baud rate. Two 8-bit latches
store the divisor in 16-bit binary format. These Divisor Latches must be loaded during initialization in order to insure
desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is
immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the DDL and DDM registers the
BRG clock is divided by 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the clock
is divided by 2 with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder
of the count. The input clock to the BRG is a 1.8462 MHz clock.
SMSC DS – FDC37N769
Page 67 of 137
Rev. 12/21/2000
SMSC [ SMSC CORPORATION ]
