PARALLEL PORT
The FDC37N769 incorporates an IBM XT/AT compatible parallel port. The FDC37N769 supports the optional PS/2
type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP)
parallel port modes. Refer to the FDC37N769 Configuration Registers and the following hardware configuration
description for information on disabling, powering down, changing the base address, and selecting the mode of
operation of the parallel port.
The FDC37N769 also incorporates SMSC’s ChiProtect™ circuitry, which prevents possible damage to the parallel
port due to printer power-up.
The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated
registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the
EPP mode. The address map and bit encoding of the Parallel Port registers is shown in
Table 62; the Parallel Port Connector is shown in Table 63.
Table 62 - Parallel Port Registers
BASE
ADDRESS
OFFSET
00H
D0
PD0
D1
PD1
D2
PD2
D3
PD3
D4
PD4
D5
PD5
D6
PD6
D7
PD7
DATA PORT1
STATUS PORT1
CONTROL PORT1
01H
02H
03H
TMOUT
0
0
nERR
SLC
SLCT
IRQE
PD4
PE
nACK nBUSY
STROBE AUTOFD
nINIT
PD2
PCD
PD5
0
0
PD0
PD0
PD0
PD0
PD0
PD1
PD1
PD1
PD1
PD1
PD3
PD6
AD7
EPP ADDR
PORT2,3
04H
05H
06H
07H
PD2
PD2
PD2
PD2
PD3
PD3
PD3
PD3
PD4
PD4
PD4
PD4
PD5
PD5
PD5
PD5
PD6
PD6
PD6
PD6
PD7
PD7
PD7
PD7
EPP DATA PORT
02,3
EPP DATA PORT
12,3
EPP DATA PORT
22,3
EPP DATA PORT
32,3
Note1
Note2
Note3
These registers are available in all modes.
These registers are only available in EPP mode.
For EPP mode, IOCHRDY must be connected to the ISA bus.
SMSC DS – FDC37N769
Page 74 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
