Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Table 59 - Individual UART Channel Register Summary Continued
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 2
Enable
Data Bit 3
Enable
Data Bit 4
0
Data Bit 5
0
Data Bit 6
0
Data Bit 7
0
Receiver Line MODEM
Status
Status
Interrupt
(ELSI)
Interrupt
(EMSI)
FIFOs
Enabled (Note
5)
Interrupt ID Bit Interrupt ID Bit
(Note 5)
0
0
FIFOs Enabled
(Note 5)
XMIT FIFO
Reset
DMA Mode
Select (Note
6)
Reserved
Reserved
RCVR Trigger RCVR Trigger
LSB
MSB
Divisor Latch
Access Bit
(DLAB)
Number of
Stop Bits
(STB)
Parity Enable Even Parity
Stick Parity Set Break
(PEN)
Select (EPS)
OUT1
OUT2
Loop
0
0
0
(Note 3)
(Note 3)
Parity Error
(PE)
Framing Error Break
(FE) Interrupt (BI) Holding
Transmitter Transmitter
Error in
Empty (TEMT) RCVR FIFO
Register
(THRE)
(Note 2)
(Note 5)
Data Carrier
Detect (DCD)
Trailing Edge Delta Data
Ring Indicator Carrier Detect Send (CTS) Ready
Clear to
Data Set
Ring Indicator
(RI)
(TERI)
(DDCD)
(DSR)
Bit 2
Bit 3
Bit 4
Bit 4
Bit 12
Bit 5
Bit 6
Bit 6
Bit 14
Bit 7
Bit 7
Bit 15
Bit 2
Bit 3
Bit 5
Bit 10
Bit 11
Bit 13
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
SMSC DS – FDC37N769
Page 70 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
