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FDC37B78X_07 参数 Datasheet PDF下载

FDC37B78X_07图片预览
型号: FDC37B78X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O控制器,支持ACPI ,实时时钟和消费性红外端口 [Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR]
分类和应用: 控制器时钟
文件页数/大小: 249 页 / 865 K
品牌: SMSC [ SMSC CORPORATION ]
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BIT  
4-6  
NAME  
DESCRIPTION  
(Note 1)  
Reserved  
WAK_STS  
Reserved. These bits always return a value of zero.  
7
This bit is set when the system is in the sleeping state and an  
enabled wakeup event occurs. This bit is set on the high-to-low  
transition of nPowerOn, if the WAK_CTRL bit in the sleep / wake  
configuration register (0xF0 in Logical Device A) is cleared. If the  
WAK_CTRL bit is set, then any enabled wakeup event will also set  
the WAK_STS bit in addition to the high-to-low transition of  
nPowerOn. It is cleared by writing a 1 to its bit location when  
nPowerOn is active (low). Upon setting this bit, the system will  
transition to the working state. (Note 1)  
Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit position  
and by Vbat POR. Writing a 0 has no effect.  
Note 2: In the present implementation of Button_In, pressing the button will always wake the machine  
(i.e., activate nPowerOn).  
Power Management 1 Enable Register 1 (PM1_EN 1)  
Register Location: <PM1_BLK>+2 System I/O Space  
Default Value:00h on Vbat POR  
Attribute:Read/Write (Note 0)  
Size:8-bits  
BIT  
0-7  
NAME  
Reserved  
DESCRIPTION  
Reserved. These bits always return a value of zero.  
Power Management 1 Enable Register 2 (PM1_EN 2)  
Register Location: <PM1_BLK>+3 System I/O Space  
Default Value:00h on Vbat POR  
Attribute:Read/Write (Note 0)  
Size:8-bits  
BIT  
NAME  
DESCRIPTION  
0
PWRBTN_EN This bit is used to enable the assertion of the Button_In to generate an  
SCI event. The PWRBTN_STS bit is set anytime the Button_In signal is  
asserted. The enable bit does not have to be set to enable the setting of  
the PWRBTN_STS bit by the assertion of the Button_In signal.  
1
2
Reserved  
RTC_EN  
Reserved.  
This bit is used to enable the setting of the RTC_STS bit to generate an  
SCI. The RTC_STS bit is set anytime the RTC generates an alarm.  
Reserved. These bits always return a value of zero.  
3-7  
Reserved  
Power Management 1 Control Register 1 (PM1_CNTRL 1)  
Register Location: <PM1_BLK>+4 System I/O Space  
Default Value:00h on Vbat POR  
Attribute:Read/Write (Note 0)  
Size:8-bits  
BIT  
NAME  
DESCRIPTION  
0
SCI_EN  
When this bit is set, then the SCI enabled power management events will  
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