When PME_EN is inactive, the nPME signal can
not be asserted. When PME_EN is asserted, any
wake source whose individual PME Wake Enable
register bit is asserted can cause nPME to
become asserted. The PME Wake Status register
indicates which wake source has asserted the
nPME signal. The PME Status bit, PME_STS, is
asserted by active transitions of PME Wake
sources. PME_STS will become asserted
independent of the state of the global PME enable,
PME_EN.
PME SUPPORT
The FDC37B78x offers support for PCI power
management events (PMEs).
management event is requested by a PCI function
via the assertion of the nPME signal. The
assertion and deassertion of nPME is
A
power
asynchronous to the PCI clock.
In the
FDC37B78x, active transitions on the ring indicator
inputs nRI1 and nRI2 or the nRING pin, valid NEC
infrared remote control frames, active keyboard-
clock edges, active mouse-clock edges, RTC
alarm, and GPIOs GP10-GP17 can directly assert
the nPME signal. In addition, if the DEVINT_EN bit
in the PME_EN 1 Register is set, and if the
EN_SMI_PME bit in the SMI_EN 2 register is set,
then any of the SMI Events can also generate a
nPME. See the SCI/PME and SMI/PME logic
diagrams in FIGURE 5 and FIGURE 6.
In the FDC37B78x the nPME pin is an open drain,
active low, driver. The FDC37B78x nPME pin is
fully isolated from other external devices that might
pull the PCI nPME signal low; i.e., the PCI nPME
signal is capable of being driven high externally by
another active device or pullup even when the the
FDC37B78x VDD is grounded, providing VTR
power is active. The FDC37B78x nPME driver
sinks 6mA at .55V max (see section 4.2.1.1 DC
Specifications, page 122, in the PCI Local Bus
Specification, Revision 2.1).
nPME functionality is controlled by the runtime
registers
at
<PM1_BLK>+Ch
through
<PM1_BLK>+11h.
The PME Enable bit,
PME_EN, globally controls PME Wake-up events.
(SCI). Any status bit in the ACPI specification
has the following attributes:
ACPI/PME/SMI REGISTERS
A.
Status bits are only set through some
defined “hardware event.”
Unless otherwise noted, Status bits are
cleared by writing a “HIGH” to that bit
position, and upon VTR POR. Writing a
0 has no effect.
Status bits only generate interrupts
while their associated bit in the enable
register is set.
Function bit positions in the status
register have the same bit position in
Logical Device A in the configuration section
contains the address pointer to the ACPI power
management register block, and PM1_BLK.
These are run-time registers; Included in the
PM1_BLK is an enable bit to allow the SCI group
interrupt to be routed to any serial interrupt or the
IRQ11 pin, or onto the nPME/SCI pin. Note: See
IRQ mux control register for SCI/PME/SMI
selection function and pin configuration bits.
B.
C.
D.
Register Description
the
enable
register
(there
are
exceptions to this rule, special status
bits have no enables).
The ACPI register model consists of a number of
fixed register blocks that perform designated
functions. A register block consists of a number
of registers that perform Status, Enable and
Control functions. The ACPI specification deals
with events (which have an associated interrupt
status and enable bits, and sometimes an
associated control function) and control features.
The status registers illustrate what defined
function is requesting ACPI interrupt services
Note that this implies that if the respective enable
bit is reset and the hardware event occurs, the
respective status bit is set, however no interrupt
is generated until the enable bit is set. This
allows software to test the state of the event (by
examining the status bit) without necessarily
generating an interrupt. There are a special class
of status bits that have no respective enable bit,
154
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