•
The PME_Status bit is read/write-clear. Writing a “1” to the PME_Status bit will clear it (if there are
no pending PME events) and cause the FDC37C78X to stop asserting the nPME, if enabled. See
Figure 5.
•
•
Writing a “0” has no effect on the PME_Status bit.
The PME_Status bit is reset to “0” during VBAT Power-On-Reset.
PME Enable Register (PME_EN)
Register Location: <PM1_BLK>+11h System I/O Space
Default Value:00h on Vbat POR
Attribute:Read/Write (Note 0)
Size:8-bits
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RESERVED
PME_En
0x00
•
•
•
Setting the PME_En bit to “1” enables the FDC37B78x to assert the nPME signal.
When the PME_En bit is reset to “0”, nPME signal assertion is disabled.
The PME_En bit is reset to “0” during VBAT Power-On-Reset.
PME Status Register 1 (PME_STS 1)
Register Location: <PM1_BLK>+Ch System I/O Space
Default Value:00h on Vbat POR
Attribute:Read/Write (Note 0)
Size:8-bits
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
DEVINT
_STS
RTC_PME
_STS
nRING
MOUSE
KBD
RI1
RI2
CIR
0x00
PME Status Register 2 (PME_STS2)
Register Location: <PM1_BLK>+Dh System I/O Space
Default Value:00h on Vbat POR
Attribute:Read/Write (Note 0)
Size:8-bits
D7
D6
D5
D4
D3
D2
D1
D0
DEFAUL
T
GP17 GP16 GP15 GP14 GP13 GP12 GP11 GP10
0x00
•
•
The PME Status registers indicate the state of the individual FDC37B78x PME wake sources,
independent of the state of the individual source enables or the PME_En bit.
If the wake source has asserted a wake event, the associated PME Status bit will be “1”. The wake
source bits in the PME Status registers are read/write-clear: an active (“1”) PME Status bit can only
be cleared by writing a “1” to the bit. Writing a “0” to bits in the PME Wake Status register has no
effect.
PME Enable Register 1 (PME_EN1)
Register Location: <PM1_BLK>+Eh System I/O Space
Default Value:00h on Vbat POR
Attribute:Read/Write (Note 0)
161
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