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FDC37B78X_07 参数 Datasheet PDF下载

FDC37B78X_07图片预览
型号: FDC37B78X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O控制器,支持ACPI ,实时时钟和消费性红外端口 [Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR]
分类和应用: 控制器时钟
文件页数/大小: 249 页 / 865 K
品牌: SMSC [ SMSC CORPORATION ]
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General Purpose Event Status Register 1 (GPE_STS1)  
Register Location: <PM1_BLK>+8 System I/O Space  
Default Value:00h on Vbat POR  
Attribute:Read/Write (Note 0)  
Size:8-bits  
BIT  
NAME  
DESCRIPTION  
0
SCI_STS1 This bit is set when the device power management events (PME events) occur.  
When enabled, the setting of this bit will generate an SCI Interrupt (Note 1).  
Writing a “1” to this bit will clear it if there are no pending PME events. See  
Figure 5.  
1-7  
Reserved  
Reserved. These bits always return a value of zero.  
Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit position  
and by Vbat POR. Writing a 0 has no effect.  
General Purpose Event Enable Register 1 (GPE_EN1)  
Register Location: <PM1_BLK>+9 System I/O Space  
Default Value:00h on Vbat POR  
Attribute:Read/Write (Note 0)  
Size:8-bits  
BIT  
NAME  
DESCRIPTION  
0
SCI_EN1 When this bit is set, then the enabled device power management events (PME  
events) will generate an SCI interrupt. When this bit is reset, device power  
management events will not generate an SCI interrupt.  
1-7  
Reserved Reserved. These bits always return a value of zero.  
Note 0: all bits described as "reserved" in writeable registers must be written with the value 0 when the  
register is written.  
PME Registers  
The power management event function has a PME_Status bit and a PME_En bit. These bits are  
defined in the PCI Bus Power Management Interface Specification, Revision 1.0, Draft, Copyright ©  
1997, PCI Special Interest Group, Mar. 18, 1997.  
The default states for the PME_Status and PME_En bits are controlled by Vbat Power-On-Reset.  
PME Status Register (PME_STS)  
Register Location: <PM1_BLK>+10h System I/O Space  
Default Value:00h on Vbat POR  
Attribute:Read/Write (Note 0)  
Size:8-bits  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
DEFAULT  
RESERVED  
PME_Status  
0x00  
The PME_Status bit is set when the FDC37B78x would normally assert the PCI nPME signal,  
independent of the state of the PME_En bit. Only active transitions on the PME Wake sources can  
set the PME_Status bit.  
160  
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