Power Button With Override
ACPI/PME/SMI FEATURES
ACPI Features
The power button has a status and and enable
bit in the PM1_BLK of registers to provide an SCI
upon the button press. The power button can
also turn the system on and off through the soft
power management logic. The power button
also has an override event as required by the
The FDC37B78x supports ACPI as described in
this section. These features comply with the
ACPI Specification, Revision 1.0.
ACPI specification.
See The Soft Power
Legacy/ACPI Select Capability
Management Section. This override event is
described as follows: If the user presses the
power button for more than 4 seconds while the
system is in the working state, a hardware event
is generated and the system will transition to the
off state. There are status and enable bits
associated with this feature in the PM1_BLK
registers.
This capability consists of an SMI/SCI switch
which is required in a system that supports both
legacy and ACPI power management models.
This is due to the fact that the system software
for legacy power management consists of the
SMI interrupt handler while for ACPI it consists of
the ACPI driver (SCI interrupt handler). This
support uses Logical Device A at 0x0A to hold
the address pointers to the ACPI power
management register block, PM1_BLK, which
consists of run-time registers. Included in the
PM1_BLK is an enable bit, SCI_EN, to allow the
SCI interrupt to be generated upon an enabled
SCI event. This SCI interrupt can be switched
out to the nPME/SCI pin or routed to one of the
parallel interrupts, IRQ11, or any Serial IRQ
frame. Note that the Serial IRQ is not available
under VTR power. The polarity and output type
(open collector or push-pull) of the SCI is
selected through the IRQ MUX Register.
RTC Alarm
The ACPI specification requires that the RTC
alarm generate a hardware wake-up event from
the sleeping state. The RTC alarm event can be
enabled as both a PME and an SCI event
through bits in the PM1_BLK of registers. In
addition, the can also turn the system on due to
the RTC alarm through the soft power
management logic.
There is a bit in the PME Enable Register and
the PME Status Register 1 to enable the RTC
alarm event as a nPME event and to read its
status. The status bit is set when the RTC
generates an alarm event and is cleared by
writing a 1 to this bit (writing a 0 has no effect).
When the RTC generates an alarm event, the
The software power management events (those
that generate an SMI in legacy mode and an SCI
in ACPI mode) are controlled by the EN_SMI and
SCI_EN bits. The SCI enable bit, SCI_EN, is
located in the PM1_CNTRL register, bit 0. This
bit is used in conjunction with EN_SMI, bit 7 of
the SMI enable register 2, to enable either SCI or
SMI (or both). For legacy power management,
the EN_SMI bit is used; if set, it routes the power
management events to the SMI interrupt logic.
For ACPI power management, the SCI_EN bit is
used; if set, it routes the power management
events to the SCI interrupt logic.
RTC_PME_STS bit will be set.
If the
RTC_PME_EN bit is set, an RTC PME power
management event will be generated.
For SCI, the RTC_STS and RTC_EN bits are in
the PM1_STS and PM1_EN registers.
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