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FDC37B78X_07 参数 Datasheet PDF下载

FDC37B78X_07图片预览
型号: FDC37B78X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O控制器,支持ACPI ,实时时钟和消费性红外端口 [Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR]
分类和应用: 控制器时钟
文件页数/大小: 249 页 / 865 K
品牌: SMSC [ SMSC CORPORATION ]
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2. However, only the enabled wakeup functions  
will turn on power to the system.  
REGISTERS  
The following registers can be accessed when in  
configuration mode at Logical Device 8,  
Registers B0-B3, B8 and F4, and when not in  
configuration they can be accessed through the  
Index and Data Register. All soft power  
management configuration registers are battery  
backed up and are reset on Vbat POR.  
Soft Power Control Registers  
WDT_CTRL  
(Configuration Register F4, Logical Device 8)  
This register is used for soft power management  
and watchdog timer control. Bits [7:5] are for soft  
power management: SPOFF, Restart_Cnt,  
Stop_Cnt.  
Soft Power Enable Registers  
Delay 2 Time Set Register  
SOFT POWER ENABLE REGISTER 1  
(Configuration Register B8, Logical Device 8)  
This register is used to set Delay 2 to value from  
500msec to 32sec. The default value is  
500msec.  
(Configuration Register B0, Logical Device 8)  
This register contains the enable bits for the  
wake-up function of the nPowerOn bit. When  
enabled, these bits allow their corresponding  
function to turn on power to the system.  
The power button has an override event as  
required by the ACPI specification. If the user  
presses the power button for more than four  
seconds while the system is in the working state,  
a hardware event is generated and the system  
will transition to the off state. There are status  
bits and enable bits associated with this feature  
SOFT POWER ENABLE REGISTER 2  
(Configuration Register B1, Logical Device 8)  
This register contains additional enable bits for  
the wake-up function of the nPowerOn bit. When  
enabled, these bits allow their corresponding  
function to turn on power to the system. It also  
contains OFF_EN: After power up, this bit  
defaults to 1, i.e., enabled. This bit allows the  
software to enable or disable the button control  
of power off.  
in the PM1_BLK registers.  
section.  
See the ACPI  
This override event utilizes power button logic to  
determine that the power button (Button_In) has  
been pressed for more that four seconds. The  
override enable/disable bit, PWRBTNOR_EN,  
allows this override function to be turned on/off.  
If enabled, this override event will result in setting  
the override status bit, PWRBTNOR_STS (to be  
cleared by writing a 1 to its bit position - writing a  
0 has no effect), clearing the regular button  
status bit, PWRBTN_STS, and generating an  
event to be routed into the soft power  
management logic to turn off the system. The  
override status bit alerts the system upon power-  
up that an override event was used to power  
down the system, and will be used to properly  
power-up the system.  
Soft Power Status Registers  
Soft Power Status Register 1  
(Configuration Register B2, Logical Device 8)  
This register contains the status for the wake-up  
events. Note: The status bit gets set if the  
wakeup event occurs, whether or not it is  
enabled as a wakeup function by setting the  
corresponding bit in Soft Power Enable Register  
1. However, only the enabled wakeup functions  
will turn on power to the system.  
Soft Power Status Register 2  
(Configuration Register B3, Logical Device 8)  
This register contains additional status for the  
wake-up events. Note: The status bit gets set if  
the wakeup event occurs, whether or not it is  
enabled as a wakeup function by setting the  
corresponding bit in Soft Power Enable Register  
Figure 11 shows the soft power management  
logic with the override timer path from the button  
input. The override timer counts while the button  
is held (in the present implementation this would  
be when the button input is high) and is cleared  
150  
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