SMI Status Register 2 (SMI_STS2)
Register Location:
Default Value:
Attribute:
<PM1_BLK>+13h System I/O Space
00h on Vbat POR
Read/Write
8-bits
Size:
NAME
DESCRIPTION
SMI Status Register 2
This register is used to read the status of the SMI inputs.
Bit[0] MINT: Mouse Interrupt. Cleared at source.
Default = 0x00
on Vbat POR
Bit[1] KINT: Keyboard Interrupt. Cleared at source.
Bit[2] IRINT: This bit is set by a transition on the IR pin (RXD2 or IRRX2 as
selected by Bit 6 of Configuration Register 0xF1 in Logical Device 5, i.e.,
after the MUX). Cleared by a read of this register.
Bit[3] BINT: Cleared by a read of this register.
Bit[4] P12: 8042 P1.2. Cleared at source
Bits[5:6] Reserved
Bit[7] SLP_EN_SMI. The SLP_EN SMI status bit. Cleared by a read of this
register. (See Sleep Enable Config Reg.)
0=no SMI due to setting SLP_EN bit
1=SMI generated due to setting SLP_EN bit.
SMI Enable Register 1 (SMI_EN1)
Register Location:
Default Value:
Attribute:
< PM1_BLK >+14h System I/O Space
00h on Vbat POR
Read/Write
8-bits
Size:
NAME
DESCRIPTION
SMI Enable Register 1
This register is used to enable the different interrupt sources onto the group
nSMI output.
Default = 0x00
on Vbat POR
1=Enable
0=Disable
Bit[0] EN_RING
Note: the PME status bit for RING is used as the SMI status bit for RING
(see PME Status Register).
Bit[1] EN_PINT
Bit[2] EN_U2INT
Bit[3] EN_U1INT
Bit[4] EN_FINT
Bit[5] EN_GPINT2
Bit[6] EN_GPINT1
Bit[7] EN_WDT
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