SMI_EN
Registers
SMI_STS
Registers
EVENT
SMI_STS1 Register
SMI_EN1 Register
RING Bit, PME_STS1 Register
nRING
EN_RING
PINT
PINT
EN_PINT
U2INT
U1INT
FINT
U2INT
U1INT
FINT
EN_U2INT
EN_U1INT
EN_FINT
GPINT2
GPINT1
WDT
GPINT2
GPINT1
WDT
EN_GPINT2
EN_GPINT1
EN_WDT
Group
SMI
nSMI
out to pin
or Serial
IRQ2
SMI_STS2 Register
SMI_EN2 Register
MINT
MINT
KINT
IRINT
BINT
P12
EN_SMI
EN_MINT
EN_KINT
EN_IRINT
EN_BINT
EN_P12
KINT
IRINT
BINT
P12
Bit 7
of SMI_EN2
Register
DEV_INT
SLP_EN_SMI
SLP_EN
to nPME
Interface
Logic
EN_SMI_PME
Bit 6 of
SLP_CTRL
SMI_EN2 Register
Bit 0 of the Sleep Enable
Configuration Register
0xF0 of Logical Device A.
Key to Symbols
Enable bit
Interrupt Status bit: Cleared at
source
Interrupt Status bit: Cleared by
a read of register
Sticky Status bit: Cleared by a
write of ‘1’ to this bit
FIGURE 8 - SMI/PME LOGIC
CONFIGURATION
157
SMSC [ SMSC CORPORATION ]
