PME Enable Register 2 (PME_EN2)
Register Location:
Default Value:
Attribute:
<PM1_BLK>+Fh System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
Size:
D7
GP17
D6
GP16
D5
GP15
D4
GP14
D3
GP13
D2
GP12
D1
GP11
D0
GP10
DEFAULT
0x00
•
•
The PME Enable registers enable the individual FDC37B72x wake sources onto the nPME bus.
When the PME Enable register bit for a wake source is active (“1”), if the source asserts a wake
event and the PME_En bit is “1”, the source will assert the PCI nPME signal.
•
When the PME Enable register bit for a wake source is inactive (“0”), the PME Status register will
indicate the state of the wake source but will not assert the PCI nPME signal.
SMI Registers
The FDC37B72x implements a group nSMI output pin. The nSMI group interrupt output consists of the
enabled interrupts from each of the functional blocks in the chip plus other SMI events. The interrupts
are enabled onto the group nSMI output via the SMI Enable Registers 1 and 2. The nSMI output is then
enabled onto the group nSMI output pin via bit[7] in the SMI Enable Register 2. These SMI events can
also be enabled as nPME/SCI events by setting the EN_SMI_PME bit, bit[6] of SMI Enable Register 2.
This register is also used to enable the group nSMI output onto the nSMI Serial/Parallel IRQ pin and the
routing of 8042 P12 internally to nSMI.
SMI Status Register 1 (SMI_STS1)
Register Location:
Default Value:
Attribute:
<PM1_BLK>+12h System I/O Space
00h on Vbat POR
Read/Write
8-bits
Size:
NAME
DESCRIPTION
SMI Status Register 1
This register is used to read the status of the SMI inputs.
Default = 0x00
on Vbat POR
The following bits must be cleared at their source.
Bit[0] Reserved
Bit[1] PINT (Parallel Port Interrupt)
Bit[2] U2INT (UART 2 Interrupt)
Bit[3] U1INT (UART 1 Interrupt)
Bit[4] FINT (Floppy Disk Controller Interrupt)
Bit[5] GPINT2 (Group Interrupt 2)
Bit[6] GPINT1 (Group Interrupt 1)
Bit[7] WDT (Watch Dog Timer)
152
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