General Purpose Event Enable Register 1 (GPE_EN1)
Register Location:
Default Value:
Attribute:
<PM1_BLK>+9 System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
Size:
BIT
NAME
DESCRIPTION
0
SCI_EN1
When this bit is set, then the enabled device power management events
(PME events) will generate an SCI interrupt. When this bit is reset,
device power management events will not generate an SCI interrupt.
Reserved. These bits always return a value of zero.
1-7
Reserved
Note 0: all bits described as "reserved" in writeable registers must be written with the value 0 when the
register is written.
PME Registers
The power management event function has a PME_Status bit and a PME_En bit. These bits are
defined in the PCI Bus Power Management Interface Specification, Revision 1.0, Draft, Copyright ©
1997, PCI Special Interest Group, Mar. 18, 1997.
The default states for the PME_Status and PME_En bits are controlled by Vbat Power-On-Reset.
PME Status Register (PME_STS)
Register Location:
Default Value:
Attribute:
<PM1_BLK>+10h System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
Size:
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RESERVED
PME_Status
0x00
•
•
The PME_Status bit is set when the FDC37B72x would normally assert the PCI nPME signal,
independent of the state of the PME_En bit. Only active transitions on the PME Wake sources can
set the PME_Status bit.
The PME_Status bit is read/write-clear. Writing a “1” to the PME_Status bit will clear it and cause
the FDC37B72x to stop asserting the nPME, if enabled.
•
•
Writing a “0” has no effect on the PME_Status bit.
The PME_Status bit is reset to “0” during VBAT Power-On-Reset.
150
SMSC [ SMSC CORPORATION ]
