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FDC37B72X_07 参数 Datasheet PDF下载

FDC37B72X_07图片预览
型号: FDC37B72X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 128引脚增强型超级I / O控制器,支持ACPI [128 Pin Enhanced Super I/O Controller with ACPI Support]
分类和应用: 控制器
文件页数/大小: 238 页 / 816 K
品牌: SMSC [ SMSC CORPORATION ]
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Power Management 1 Enable Register 1 (PM1_EN 1)  
Register Location:  
Default Value:  
Attribute:  
<PM1_BLK>+2 System I/O Space  
00h on Vbat POR  
Read/Write (Note 0)  
8-bits  
Size:  
BIT  
0-7  
NAME  
Reserved  
DESCRIPTION  
Reserved. These bits always return a value of zero.  
Power Management 1 Enable Register 2 (PM1_EN 2)  
Register Location:  
Default Value:  
Attribute:  
<PM1_BLK>+3 System I/O Space  
00h on Vbat POR  
Read/Write (Note 0)  
8-bits  
Size:  
BIT  
NAME  
DESCRIPTION  
0
PWRBTN_EN  
This bit is used to enable the assertion of the Button_In to  
generate an SCI event. The PWRBTN_STS bit is set anytime  
the Button_In signal is asserted. The enable bit does not  
have to be set to enable the setting of the PWRBTN_STS bit  
by the assertion of the Button_In signal.  
1-7  
Reserved  
Reserved. These bits always return a value of zero.  
Power Management 1 Control Register 1 (PM1_CNTRL 1)  
Register Location:  
Default Value:  
Attribute:  
<PM1_BLK>+4 System I/O Space  
00h on Vbat POR  
Read/Write (Note 0)  
8-bits  
Size:  
BIT  
NAME  
DESCRIPTION  
0
SCI_EN  
When this bit is set, then the enabled SCI power management  
events generate an SCI interrupt. When this bit is reset power  
management events do not generate an SCI interrupt.  
Reserved. These bits always return a value of zero.  
1-7  
Reserved  
148  
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