nBINT
OFF_EN
OFF_DLY
Delay2
nSPOFF1
Logic
Button
nSPOFF
L
VTR_POR_EN
VTR POR
Logic
AL_REM_EN
Alarm
Button Input
ED; PG
OFF_DLY
Delay1
VTR
SP1
SPx
ED; L
EN1
Flip
Flop 1
D
nPowerOn
nSPOFF1
Q
CLR
Open Collector
Type Output
TR_
V
POR_OFF
VTR POR
POR
ED; L
BAT
V
ENx
nSPOFF1
Soft Power
Off nSPOFF1
Logic
TR
V
POR With
Vbat<1.2V
Override
Timer
PWRBTNOR_STS
PWRBTNOR_EN
nPowerOn output to go active low.
A transition on the Button input, or on any enabled SPx inputs causes the
A low pulse on the Soft Power Off signal, a Vbat POR, a VTR POR with Vbat<1.2V, or Power Button Override Event causes
nPowerOn to float.
ED;PG = Edge Detect, Pulse Generator
ED;L = Edge Detect and Latch
FIGURE 5 - SOFT POWER MANAGEMENT FUNCTIONAL DIAGRAM
Note 1: All soft power management functions run off of VTR. When VTR is not present, Vbat supplies
power to Flip Flop 1.
Note 2: Flip Flop 1 is battery backed-up so that it returns the last valid state of the machine.
Note 3: A battery backed-up enable bit in the alarm control register can be set to force Flip Flop 1 to come
up ‘off’ after a VTR POR, the VTR_POR_OFF bit. A similar bit can be set to force Flip Flop 1 to
come up ‘on’ after a VTR POR, the VTR_POR_EN bit. These bits are in the Soft Power Enable
Register 2 in Logical Device 8 at 0xB1, defined as follows.
Bit 4 – VTR_POR_OFF
If VTR_POR_OFF is set, the nPowerOn pin will go inactive (float) and the main power (Vcc) will
remain off when the VTR POR occurs. The software must not set VTR_POR_OFF and
VTR_POR_EN at the same time.
BIT 6 - VTR_POR_EN
If VTR_POR_EN is set, the nPowerOn pin will go active (low) and the machine will power-up as
soon as a VTR POR occurs. The software must not set VTR_POR_OFF and VTR_POR_EN at
the same time.
REGISTERS
137
SMSC [ SMSC CORPORATION ]
