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FDC37B72X_07 参数 Datasheet PDF下载

FDC37B72X_07图片预览
型号: FDC37B72X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 128引脚增强型超级I / O控制器,支持ACPI [128 Pin Enhanced Super I/O Controller with ACPI Support]
分类和应用: 控制器
文件页数/大小: 238 页 / 816 K
品牌: SMSC [ SMSC CORPORATION ]
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The following registers can be accessed when in  
configuration mode at Logical Device 8,  
Registers B0-B3, B8 and F4, and when not in  
configuration they can be accessed through the  
Index and Data Register. All soft power  
management configuration registers are battery  
backed up and are reset on Vbat POR.  
(Configuration Register B2, Logical Device 8)  
This register contains the status for the wake-up  
events. Note: The status bit gets set if the  
wakeup event occurs, whether or not it is  
enabled as a wakeup function by setting the  
corresponding bit in Soft Power Enable Register  
1. However, only the enabled wakeup functions  
will turn on power to the system.  
Soft Power Enable Registers  
Soft Power Status Register 2  
(Configuration Register B3, Logical Device 8)  
This register contains additional status for the  
wake-up events. Note: The status bit gets set if  
the wakeup event occurs, whether or not it is  
enabled as a wakeup function by setting the  
corresponding bit in Soft Power Enable Register  
2. However, only the enabled wakeup functions  
will turn on power to the system.  
Soft Power Enable Register 1  
(Configuration Register B0, Logical Device 8)  
This register contains the enable bits for the  
wake-up function of the nPowerOn bit. When  
enabled, these bits allow their corresponding  
function to turn on power to the system.  
Soft Power Enable Register 2  
(Configuration Register B1, Logical Device 8)  
This register contains additional enable bits for  
the wake-up function of the nPowerOn bit. When  
enabled, these bits allow their corresponding  
function to turn on power to the system. It also  
Soft Power Control Registers  
WDT_CTRL  
(Configuration Register F4, Logical Device 8)  
This register is used for soft power management  
and watchdog timer control. Bits [7:5] are for soft  
power management: SPOFF, Restart_Cnt,  
Stop_Cnt.  
contains  
the  
VTR_POR_EN  
and  
VTR_POR_OFF bits, as well as the OFF_EN bit,  
which is defined as follows: After power up, this  
bit defaults to 1, i.e., enabled. This bit allows the  
software to enable or disable the button control  
of power off.  
Delay 2 Time Set Register  
(Configuration Register B8, Logical Device 8)  
This register is used to set Delay 2 to value from  
500msec to 32sec. The default value is  
500msec.  
Soft Power Status Registers  
Soft Power Status Register 1  
138  
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