SOFT POWER MANAGEMENT
This chip employs soft power management to
be programmed to always stay off when the AC
power returns if the VTR_POR_OFF bit is
enabled. These bits are located in the Soft Power
Enable Register 2 in Logical Device 8 at 0xB1.
allow the chip to enter low power mode and to
provide a variety of wakeup events to power up
the chip. This technique allows for software
control over powerdown and wakeup events. In
low power mode, the chip runs off of the trickle
voltage, VTR. In this mode, the chip is ready to
power up from either the power button or from one
of a number of wakeup events including pressing a
key, touching the mouse or receiving data from
one of the UARTs. The alarm can also be set to
power up the system at a predetermined time to
perform one or more tasks.
The Button input can be used to turn off the power
supply after a debounce delay. The power supply
can also be turned off under software control (via a
write to register WDT_CTRL with bit 7 set).
Configuration registers L8-CR_B0 and L8-
CR_B1 select the wake-up events (SPx). The
Configuration registers L8-CR_B2 and L8-
CR_B3 indict the wake-up event status. The
possible wake-events are:
The implementation of Soft Power Management is
illustrated in Figure 11. A high to low transition on
the Button input or on any of the enabled wakeup
events (SPx) causes the nPowerOn output to go
active low which turns on the main power supply.
Even if the power supply is completely lost (i.e.,
VTR is not present) the power supply can still be
turned on upon the return of VTR. This is
accomplished by a VTR power on reset if the
VTR_POR_EN bit is enabled. The chip can also
UART1 and UART 2 Ring Indicator Pin
Keyboard and Mouse clock Pin
Group Interrupt 1, Group Interrupt 2
IRRX2 input pin
UART 1 and UART 2 Receive Data Pin
nRING pin
Power Button input pin
VTR_POR
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