signal is 1, the output tristates: an external pull-up
can pull the pin high, and the pin can be shared
i.e., P17 and nSMI can be externally tied together.
In 8042 mode, the pins cannot be programmed as
input nor inverted through the GP configuration
registers.
0ns
250ns
500ns
CLK
AEN
nAEN
64=I/O Addr
n64
nIOW
nA
DD1
nDD1
nCNTL
nIOW'
nIOW+n64
AfterD1
nAfterD1
60=I/O Addr
n60
nIOW+n60=B
nAfterD1+B
D[1]
GA20
Gate A20 Turn-On Sequence Timing
When writing to the command and data port with
time is only required to be met when using
hardware speedup; the data must be valid a
minimum of 0 nsec from the leading edge of the
write and held throughout the entire write cycle.
hardware speedup, the IOW timing shown in the
figure titled “IOW Timing for Port 92” in the
Timing Diagrams Section is used. This setup
136
SMSC [ SMSC CORPORATION ]
