ACPI/PME/SMI FEATURES
Power Button With Override
ACPI FEATURES
The power button has a status and and enable
bit in the PM1_BLK of registers to provide an SCI
upon the button press. The power button can
also turn the system on and off through the soft
power management logic. The power button
also has an override event as required by the
The FDC37B72x supports ACPI as described in
this section. These features comply with the
ACPI Specification, Revision 1.0.
Legacy/ACPI Select Capability
ACPI specification.
See The Soft Power
This capability consists of an SMI/SCI switch
which is required in a system that supports both
legacy and ACPI power management models.
This is due to the fact that the system software
for legacy power management consists of the
SMI interrupt handler while for ACPI it consists of
the ACPI driver (SCI interrupt handler). This
support uses Logical Device A at 0x0A to hold
the address pointers to the ACPI power
management register block, PM1_BLK, which
consists of run-time registers. Included in the
PM1_BLK is an enable bit, SCI_EN, to allow the
SCI interrupt to be generated upon an enabled
SCI event. This SCI interrupt can be switched
out to the nPME/SCI pin or routed to one of the
parallel interrupts. The polarity and output type
(open collector or push-pull) of the SCI is
selected through the IRQ MUX Register.
Management Section. This override event is
described as follows: If the user presses the
power button for more than 4 seconds while the
system is in the working state, a hardware event
is generated and the system will transition to the
off state. There are status and enable bits
associated with this feature in the PM1_BLK
registers.
General Purpose ACPI Events
The General Purpose ACPI events are enabled
through the SCI_EN1 bit in the GPE_EN register.
This bit, if set, allows any of the enabled PME
events to generate an SCI. In addition, if the
DEVINT_EN bit in the PME_EN 1 Register is set,
and if the EN_SMI_PME bit in the SMI_EN 2
register is set, then any of the SMI Events can
also generate an SCI. See the SCI/PME and
SMI/PME logic diagrams below.
The software power management events (those
that generate an SMI in legacy mode and an SCI
in ACPI mode) are controlled by the EN_SMI and
SCI_EN bits. The SCI enable bit, SCI_EN, is
located in the PM1_CNTRL register, bit 0. This
bit is used in conjunction with EN_SMI, bit 7 of
the SMI enable register 2, to enable either SCI or
SMI (or both). For legacy power management,
the EN_SMI bit is used; if set, it routes the power
management events to the SMI interrupt logic.
For ACPI power management, the SCI_EN bit is
used; if set, it routes the power management
events to the SCI interrupt logic.
Device Sleep States
Each device in the FDC37B72x supports two
device sleep states, D0 (on) and D3 (off). With
all devices off, the part is powered either by main
power (Vcc) or standby power (Vtr), depending
on the system sleep state. In both cases, the
part can provide wakeup capability through the
soft power management logic and generate a
nPME or nSCI. In an ACPI system, the devices
are powered on and off through control methods.
141
SMSC [ SMSC CORPORATION ]
