(as above). However, as the oscillator cell will
require an initialization time, either RESET must
be held active for sufficient time to allow the
oscillator to stabilize. Program execution will
resume as above.
Host I/F Data Register
The Input Data and Output Data registers are
each 8 bits wide. A write to this 8 bit register will
load the Keyboard Data Read Buffer, set the OBF
flag and set the KIRQ output if enabled. A read of
this register will read the data from the Keyboard
Data or Command Write Buffer and clear the IBF
flag. Refer to the KIRQ and Status register
descriptions for more information.
INTERRUPTS
The FDC37B72x provides the two 8042 interrupts,
the IBF and the Timer/Counter Overflow.
MEMORY CONFIGURATIONS
Host I/F Status Register
The FDC37B72x provides 2K of on-chip ROM and
256 bytes of on-chip RAM.
The Status register is 8 bits wide. Table 58 shows
the
contents
of
the
Status
register.
Register Definitions
TABLE 58 - STATUS REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
UD
UD
UD
UD
C/D
UD
IBF
OBF
cleared.
There is no output pin
Status Register
associated with this internal signal.
This register is cleared on a reset. This register is
read-only for the Host and read/write by the
FDC37B72x CPU.
OBF
(Output Buffer Full) - This flag is set to
whenever the FDC37B72x CPU write to
the output data register (DBB). When the
host system reads the output data
register, this bit is automatically reset.
UD
Writable by FDC37B72x CPU. These
bits are user-definable.
C/D
(Command Data)-This bit specifies
whether the input data register contains
data or a command (0 = data, 1 =
EXTERNAL CLOCK SIGNAL
The FDC37B72x Keyboard Controller clock source
is a 12 MHz clock generated from a 14.318 MHz
clock. The reset pulse must last for at least 24 16
MHz clock periods. The pulse-width requirement
applies to both internally (Vcc POR) and externally
generated reset signals. In powerdown mode, the
external clock signal is not loaded by the chip.
command).
During
a
host
data/command write operation, this bit is
set to "1" if SA2 = 1 or reset to "0" if SA2
= 0.
IBF
(Input Buffer Full)- This flag is set to 1
whenever the host system writes data
into the input data register. Setting this
flag activates the FDC37B72x CPU's
nIBF (MIRQ) interrupt if enabled. When
the FDC37B72x CPU reads the input
data register (DBB), this bit is
automatically reset and the interrupt is
DEFAULT RESET CONDITIONS
The FDC37B72x has one source of reset: an
external reset via the RESET_DRV pin. Refer to
Table 59 for the effect of each type of reset on the
internal registers.
TABLE 59 - RESETS
HARDWARE RESET (RESET)
DESCRIPTION
131
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