Dual RPM-Based PWM Fan Controller
Datasheet
5.11
Gain Registers
Table 5.17 Gain Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Gain 1
Register
35h
45h
R/W
R/W
-
-
GAIND1[1:0]
GAIND2[1:0]
GAINI1[1:0]
GAINI2[1:0]
GAINP1[1:0]
GAINP2[1:0]
2Ah
Gain 2
Register
-
-
2Ah
The Gain registers store the gain terms used by the proportional and integral portions of each of the
RPM-based Fan Speed Control Algorithms. These gain terms are used as the KD, KI, and KP gain
terms in a classic PID control solution.
Bits 5 - 4 - GAINDX[1:0] - Controls the derivative gain term used by the FSC algorithm as shown in
Table 5.18.
Bits 3-2 - GAINIX[1:0] - Controls the integral gain term used by the FSC algorithm as shown in
Table 5.18.
Bits 1-0 - GAINP[1:0] - Controls the proportional gain term used by the FSC algorithm as shown in
Table 5.18.
Table 5.18 Gain Decode
GAIND OR GAINP OR GAINI [1:0]
1
0
RESPECTIVE GAIN FACTOR
0
0
1
1
0
1
0
1
1x
2x
4x (default)
8x
5.12
Fan Spin Up Configuration Registers
Table 5.19 Fan Spin Up Configuration Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Fan 1 Spin Up
Configuration
DRIVE_FAIL_
CNT1 [1:0]
SPINUP_TIME
1 [1:0]
36h
46h
R/W
NOKICK1
SPIN_LVL1[2:0]
SPIN_LVL2[2:0]
19h
Fan 2 Spin up
Configuration
DRIVE_FAIL_
CNT2 [1:0]
SPINUP_TIME
2 [1:0]
R/W
NOKICK2
19h
The Fan Spin Up Configuration registers control the settings of Spin Up Routine. The Fan Spin Up
Configuration registers are software locked.
Bit 7 - 6 - DRIVE_FAIL_CNTx[1:0] - Determines how many update cycles are used for the Drive Fail
detection function as shown in Table 5.20. This circuitry determines whether the fan can be driven to
the desired tach target.
SMSC EMC2302
Revision 1.1 (10-12-09)
DATA3S3HEET
SMSC [ SMSC CORPORATION ]
