Dual RPM-Based PWM Fan Controller
Datasheet
Bits 3-2 - PWM_BASE2[1:0] - Determines the base frequency of the PWM2 driver.
Bits 1-0 - PWM_BASE1[1:0] - Determines the base frequency of the PWM1 driver.
Table 5.7 PWM_BASEx[1:0] Bit Decode
PWM_BASEX[1:0]
1
0
BASE FREQUENCY
0
0
1
1
0
1
0
1
26.00kHz (default)
19.531kHz
4,882Hz
2,441Hz
5.7
Fan Setting Registers
Table 5.8 Fan Driver Setting Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
30h
40h
R/W
R/W
Fan 1 Setting
Fan 2 Setting
128
128
64
64
32
32
16
16
8
8
4
4
2
2
1
1
00h
00h
The Fan Setting register always displays the current setting of the respective fan driver. Reading from
any of the registers will report the current fan speed setting of the appropriate fan driver regardless of
the operating mode. Therefore it is possible that reading from this register will not report data that was
previously written into this register.
While the RPM-based Fan Speed Control Algorithm is active, the register is read only. Writing to the
register will have no effect and the data will not be stored.
The contents of the register represent the weighting of each bit in determining the final output voltage.
The output drive for a PWM output is given by Equation [1].
VALUE
⎛
⎝
⎞
--------------------
Drive =
× 100%
[1]
⎠
255
5.8
PWM Divide Registers
Table 5.9 PWM Divide Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
31h
41h
R/W
R/W
Fan 1 Divide
Fan 2 Divide
128
128
64
64
32
32
16
16
8
8
4
4
2
2
1
1
01h
01h
The PWM Divide registers determine the final frequency of the respective PWM Fan Driver. Each driver
base frequency is divided by the value of the respective PWM Divide Register to determine the final
SMSC EMC2302
Revision 1.1 (10-12-09)
DATA2S9HEET
SMSC [ SMSC CORPORATION ]
