Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
Table 8.52 TACH Option Register Bits
R/W DEFAULT DESCRIPTION
‘0’ - Force TACH reading register to FFFEh if number of tach edges
BIT
NAME
0
SLOW
R/W
0
detected is greater than 0 but less than the programmed number of
edges
‘1’ - Force TACH reading register to FFFFh if number of tach edges
detected is greater than 0 but less than the programmed number of
edges
1
2
EDG0
EDG1
R/W
R/W
0
1
Determines the number of edges necessary for a valid TACH reading.
00 = 2 edges
01 = 3 edges
10 = 5 edges
11 = 9 edges
3
4
MODE
3EDG
R/W
R/W
0
0
Determines TACH reading mode
‘0’ Mode 1 - standard operating mode
‘1’ Mode 2 - only check measure TACH while PWM output is high.
This bit is used when the TACH Mode is configured for Mode 2 only.
‘0’ - don’t ignore 1st 3 TACH edges after PWM transitions from low to
high
‘1’ - ignore first 3 edges after guard time
Note:
This bit has been added to support a small sampling of fans that
emit irregular tach pulses when the PWM transitions ‘ON’.
Typically, the guard time is sufficient for most fans.
5
6
7
RES
RES
RES
R/W
R/W
R/W
0
0
0
Reserved
Reserved
Reserved
8.2.28
Registers 94h-96h: PWMx Option Registers
Table 8.53 Registers 94h-96h: PWMx Option Registers
Register
Address
Read/
Write
Register
Name
Bit 7
(MSb)
Bit 0
(LSb)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
94h
95h
96h
R/W
R/W
R/W
PWM1 Option
PWM2 Option
PWM3 Option
RES
RES
RES
RES
RES
RES
OPP
OPP
OPP
GRD1
GRD1
GRD1
GRD0
GRD0
GRD0
SZEN
SZEN
SZEN
UPDT1
UPDT1
UPDT1
UPDT0
UPDT0
UPDT0
0Ch
0Ch
0Ch
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
SMSC EMC2300
Revision 0.2 (06-14-06)
DATA7S3HEET
SMSC [ SMSC CORPORATION ]
