Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
9.2
SMBus Interface
tHD;STA
tLOW
tR
tF
SCLK
tSU;STA
tHD;STA
tHD;DAT
tSU;STO
tHIGH
tSU;DAT
SDA
tBUF
P
S
S
P
Figure 9.4 SMBus Timing
Table 9.2 SMBus Timing
LIMITS
SYMBOL
Fsmb
PARAMETER
MIN
MAX
UNITS
COMMENTS
SMB Operating Frequency
Spike Suppression
10
400
50
kHz
ns
Note 9.5
Note 9.6
Tsp
Tbuf
Bus free time between Stop and Start
Condition
1.3
0.6
μs
Thd:sta
Hold time after (Repeated) Start Condition.
After this period, the first clock is
generated.
μs
Tsu:sta
Tsu:sto
Thd:dat
Tsu:dat
Tlow
Thigh
Tf
Repeated Start Condition setup time
Stop Condition setup time
Data hold time
0.6
0.6
0.3
μs
μs
μs
ns
μs
μs
ns
ns
pF
0.9
Data setup time
100
1.3
0.6
Note 9.7
Clock low period
Clock high period
Clock/Data Fall Time
Clock/Data Rise Time
Capacitive load for each bus line
20+0.1Cb
20+0.1Cb
300
300
400
Tr
Cb
Note 9.5 The SMBus timing (e.g., max clock frequency of 400kHz) specified exceeds that specified
in the System Management Bus Specification, Rev 1.1. This corresponds to the maximum
clock frequency for fast mode devices on the I2C bus. See “The I2C Bus Specification,”
version 2.0, Dec. 1998.
Note 9.6 At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input
filter.
Note 9.7 If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns
(1000 ns (TR max) + 250 ns (TSU:DAT min) @ 100 kHz) before the SCLK line is released.
Revision 0.2 (06-14-06)
SMSC EMC2300
DATA7S6HEET
SMSC [ SMSC CORPORATION ]
