Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
Table 8.43 Configuration Register Bits
R/W DEFAULT DESCRIPTION
Determines functionality of the TACH3/INT# pin.
BIT
NAME
0
T3INT
R/W
0
‘0’ - TACH3 input
‘1’- INT# output
1
P2INT
R/W
0
Determines the functionality of the PWM2/INT# pin.
‘0’ - PWM2 output.
‘1’ - INT# output.
2
3
Reserved
TRDY
R/W
R
0
0
Reserved
Temperature Reading Ready - indicates that the temperature reading
registers hold valid values.
4
5
6
7
SUREN
SMSC
SMSC
INIT
R/W
R/W
R/W
R/W
1
0
0
0
Spin-up reduction enable - when set, this bit enables the reduction of the
spin-up time based on feedback from all fan tachometers associated with
each PWM.
SMSC - Writing to this bit to a value different from the default value may
cause unwanted results.
SMSC - Writing this bit to a value different than the default value may
cause unwanted results.
Setting the INIT bit to ‘1’ performs a soft reset. This bit is self-clearing.
Soft Reset sets all the registers except the Reading Registers to their
default values.
This register contains the following bits:
8.2.23
Register 80h: Interrupt Enable 2 Register
Table 8.44 Register 80h: Interrupt Enable 2 Register
Register
Address
Read/
Write
Bit 7
(MSb)
Bit 0
(LSb)
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
80h
R/W
Interrupt Enable 2 (Fan
Tachs)
RES
RES
RES
TACH4
TACH3
TACH2
TACH1
TACH
1Eh
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to enable individual fan tach error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group fan tach enable bit (Bit[0] TACH),
which is used to enable fan tach events to force the interrupt pin (INT#) low if interrupts are enabled
(see Bit[2] INTEN of the Special Function register at offset 7Ch).
See Figure 6.3 Interrupt Control on page 24.
This register contains the following bits:
SMSC EMC2300
Revision 0.2 (06-14-06)
DATA6S9HEET