Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
PWM2, PWM3
Since the test mode is XOR tree, the order of the signals in the tree is not important. SDA and SCL
are not included in the test tree.
8.2.20
Register 7Ch: Special Function Register
Table 8.37 Register 7Ch: Special Function Register
Register
Address
Read/
Write
Bit 7
(MSb)
Bit 0
(LSb)
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
7Ch
R/W
Special Function
AVG2
AVG1
AVG0
SMSC
SMSC
INTEN
MONMD
LPMD
40h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
This register contains the following bits:
Table 8.38 Special Function Register
BIT
NAME
R/W DEFAULT
DESCRIPTION
0
LPMD
R/W
0
0
Low Power Mode Select.
‘0’ = Sleep Mode
‘1’ = Low Power Mode
1
MONMD
R/W
Monitoring Mode Select.
‘0’ = Continuous Mode
‘1’ = Cycle Mode
2
3
INTEN
SMSC
R/W
R/W
0
0
Global Interrupt enable. When set enables the INT# pin output function.
SMSC - writing this bit may have undesired affects.
4
SMSC
R/W
0
SMSC - writing this bit may have undesired affects.
5
6
7
AVG0
AVG1
AVG2
R/W
R/W
R/W
0
1
0
The AVG[2:0] bits determine the amount of averaging for each of the six
measurements that are performed by the hardware monitor before the
reading registers are updated (Table 8.39, "AVG[2:0] Bit Decoder"). The
AVG[2:0] bits are priority encoded where the most significant bit has
highest priority. For example, when the AVG2 bit is asserted, 32 averages
will be performed for each measurement before the reading registers are
updated regardless of the state of the AVG[1:0] bits.
Note:
The default for the AVG[2:0] bits is ‘010’b
.
Table 8.39 AVG[2:0] Bit Decoder
AVERAGES PER READING
SFTR[7:5]
AVG1
ALL VOLTAGE
READINGS
AVG2
AVG0
REM DIODE 1 REM DIODE 2
INTERNAL DIODE
( VCCP, AND VCC)
0
0
0
1
0
0
1
X
0
1
128
16
128
16
8
1
8
1
X
X
16
16
16
32
16
32
32
32
SMSC EMC2300
Revision 0.2 (06-14-06)
DATA6S7HEET
SMSC [ SMSC CORPORATION ]
