5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
AD0-AD2,
D3-D7
VALID
VALID DATA
t1
t2,
t4
nCS
t3
t10
t9
ALE
t7
t5
nWR
t6
Note 2
t8**
t8
t12
t11
Note 3
nRD
t13
min
Parameter
max
units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
20
10
10
10
15
30
10
Valid Data Setup to nDS High
Data Hold from nDS High
Cycle Time (nWR
to Next
)**
4TARB
*
ALE High Width
ALE Low Width
nWR Low Width
nWR High Width
20
20
20
20
20
nRD
to nWR Low
*
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Note 1:
**
Note 2:
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3:
Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
FIGURE 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE
SMSC COM20020I 3.3V
Page 51
Revision 12-06-06
DATASHEET
SMSC [ SMSC CORPORATION ]
