5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
9.0 TIMING DIAGRAMS
AD0-AD2,
VALID
VALID DATA
D3-D7
t1
t2,
t4
nCS
t3
t12
t11
ALE
nDS
t6
t7
t13
t5
t14
Note 2
t8
t9
t10
DIR
MUST BE: RBUSTMG bit = 0
Parameter
min
max
units
t1
t2
t3
t4
t5
t6
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
20
10
10
10
15
40
20
nDS Low to Valid Data
0
4TARB*
10
10
20
20
60
20
t7 nDS High to Data High Impedance
t8 Cycle Time (nDS Low to Next Time Low)
t9 DIR Setup to nDS Active
t10 DIR Hold from nDS Inactive
t11 ALE High Width
t12 ALE Low Width
t13 nDS Low Width
t14 nDS High Width
*
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 2:
Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
FIGURE 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE
Revision 12-06-06
48
SMSC COM20020I 3.3V
DATASHEET
SMSC [ SMSC CORPORATION ]
