5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
VALID
A0-A2
t1
t2
t4
nCS
t3
t5
Note 3
t10
nRD
t8
t9
Note 2
t6
t7
nWR
D0-D7
VALID DATA
CASE 2: RBUSTMG bit = 1
Parameter
min
max
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
-5
0
-5
0
Address Setup to nRD Active
t1
t2
t3
t4
t5
t6
t7
t8
t9
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
nRD Low Width
4TARB*+30
60**
20
0
100
30
nRD High Width
t10
nWR
to nRD Low
20
*
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
** t6 is measured from the latest active (valid) timing among nCS, nRD, A0-A2.
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
Note 1:
should be doubled when considering back-to-back COM20020 cycles.
Note 2:
Note 3:
Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
FIGURE 16 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
SMSC COM20020I 3.3V
Page 53
Revision 12-06-06
DATASHEET
SMSC [ SMSC CORPORATION ]
