5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
AD0-AD2,
D3-D7
VALID DATA
VALID
t1
t2,
t4
nCS
t3
t10
ALE
nRD
t9
t6
t7
t5
t8
t11
nWR
t13
Note 3
t12
Note 2
MUST BE: RBUSTMG bit = 0
Parameter
min
max
units
t1
t2
t3
t4
t5
t6
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nRD Low
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
20
10
10
10
15
40
20
nRD Low to Valid Data
0
4TARB*
20
20
60
t7 nRD High to Data High Impedance
t8
t9
t10
t11
t12
t13
Cycle Time (nRD Low to Next Time Low)
ALE High Width
ALE Low Width
nRD Low Width
nRD High Width
20
20
nWR
to nRD Low
*
T
ARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
ARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
T
Note 1:
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 2:
Note 3:
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
FIGURE 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
SMSC COM20020I 3.3V
Page 49
Revision 12-06-06
DATASHEET
SMSC [ SMSC CORPORATION ]
