5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Table 6.6 - Address Pointer High Register
BIT
BIT NAME
Read Data
SYMBOL
RDDATA
DESCRIPTION
7
This bit tells the COM20020ID whether the following access will
be a read or write. A logic "1" prepares the device for a read, a
logic "0" prepares it for a write.
6
Auto Increment
AUTOINC
A10-A8
This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic increment of
the pointer after each access, while a logic "0" disables this
function. Please refer to the Sequential Access Memory section
for further detail.
5-3
2-0
(Reserved)
These bits are undefined.
Address 10-8
These bits hold the upper three address bits which provide
addresses to RAM.
Table 6.7 - Address Pointer Low Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
7-0
Address 7-0
A7-A0
These bits hold the lower 8 address bits which provide the
addresses to RAM.
Table 6.8 - Sub Address Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
7-3
Reserved
These bits are undefined.
2,1,0 Sub Address 2,1,0
SUBAD
2,1,0
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2
SUBAD1
SUBAD0
Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Tentative ID \ (Same
Node ID
Setup 1
\ as in
/ Config
/ Register)
Next ID
Setup 2
Reserved
Reserved
Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by writing
the Configuration Register.
Revision 12-05-06
Page 34
SMSC COM20020I Rev D
DATASHEET
SMSC [ SMSC CORPORATION ]
