5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Table 6.11 - Setup 2 Register
SYMBOL DESCRIPTION
BIT
BIT NAME
7
Read Bus Timing
Select
RBUSTMG
This bit is used to Disable/Enable the High Speed CPU Read
function for High Speed CPU bus support. RBUSTMG=0: Disable
(Default), RBUSTMG=1: Enable. It does not influence write
operation. High speed CPU Read operation is only for non-
multiplexed bus.
6
Reserved
This bit is undefined.
5,4
Clock Multiplier
CKUP1, 0
Higher frequency clocks are generated from the 20 MHz crystal
through the selection of these two bits as shown. This clock
multiplier is powered-down on default. After changing the CKUP1
and CKUP0 bits, the ARCNET core operation is stopped and the
internal PLL in the clock multiplier is awakened and it starts to
generate the 40 MHz. The lock out time of the internal PLL is 8μSec
typically. After 1 mS it is necessary to write command data '18H' to
command register for re-starting the ARCNET core operation. EF
bit must be ‘1’ if the data rate is over 5Mbps.
CAUTION: Changing the CKUP1 and CKUP0 bits must be one
time or less after releasing a hardware reset.
CKUP1
CKUP0
Clock Frequency (Data Rate)
20 MHz (Up to 2.5Mbps) Default
40 MHz (Up to 5Mbps)
Reserved
0
0
1
1
0
1
0
1
Reserved
Note: After changing the CKUP1 or CKUP0 bits, it is necessary to
write a command data '18H' to the command register.
Because after changing the CKUP [1, 0] bits, the internal
operation is stopped temporarily. The writing of the
command is to start the operation.
These initializing steps are shown below.
Hardware reset (Power ON)
Change CKUP[1, 0] bit
Wait 1mSec (wait until stable oscillation)
Write command '18H' (start internal operation)
Start initializing routine (Execute existing software)
3
2
Enhanced Functions
EF
This bit is used to enable the new enhanced functions in the
COM20020ID. EF = 0: Disable (Default), EF = 1: Enable. If EF = 0,
the timing and function is the same as in the COM20020, Revision
B. See Appendix A. EF bit must be ‘1’ if the data rate is over
5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
No Synchronous
NOSYNC
This bit is used to enable the SYNC command during initialization.
NOSYNC= 0, Enable (Default) The line must be idle for the RAM
initialization sequence to be written. NOSYNC= 1, Disable:) The line
does not have to be idle for the RAM initialization sequence to be
written. See Appendix A.
SMSC COM20020I Rev D
Page 37
Revision 12-05-06
DATASHEET
SMSC [ SMSC CORPORATION ]
