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COM20020I-DZD 参数 Datasheet PDF下载

COM20020I-DZD图片预览
型号: COM20020I-DZD
PDF下载: 下载PDF文件 查看货源
内容描述: 5Mbps的ARCNET ( ANSI 878.1 )控制器2K ×8片内RAM [5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输局域网时钟
文件页数/大小: 72 页 / 406 K
品牌: SMSC [ SMSC CORPORATION ]
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5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM  
Datasheet  
Table 6.10 - Setup 1 Register  
SYMBOL  
P1MODE  
BIT  
BIT NAME  
Pulse1 Mode  
DESCRIPTION  
7
This bit determines the type of PULSE1 output driver used in  
Backplane Mode. When high, a push/pull output is used. When  
low, an open drain output is used. The default is open drain.  
6
Four NACKS  
FOUR  
NACKS  
This bit, when set, will cause the EXNACK bit in the Diagnostic  
Status Register to set after four NACKs to Free Buffer Enquiry are  
detected by the COM20020ID. This bit, when reset, will set the  
EXNACK bit after 128 NACKs to Free Buffer Enquiry. The default  
is 128.  
5
4
Reserved  
Do not set.  
Receive All  
RCVALL  
This bit, when set, allows the COM20020ID to receive all valid  
data packets on the network, regardless of their destination ID.  
This mode can be used to implement a network monitor with the  
transmitter on- or off-line. Note that ACKs are only sent for  
packets received with a destination ID equal to the COM20020ID's  
programmed node ID. This feature can be used to put the  
COM20020ID in a 'listen-only' mode, where the transmitter is  
disabled and the COM20020ID is not passing tokens. Defaults  
low.  
3,2,1 Clock Prescaler Bits  
CKP3,2,1  
These bits are used to determine the data rate of the  
COM20020ID. The following table is for a 20 MHz crystal: (Clock  
Multiplier is bypassed)  
3,2,1  
CKP3  
CKP2 CKP1 DIVISOR  
SPEED  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
8
2.5Mbs  
16  
32  
64  
128  
1.25Mbs  
625Kbs  
312.5Kbs  
156.25Kbs  
NOTE: The lowest data rate achievable by the COM20020ID is  
156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock Multiplier output  
clock speed greater than 20 MHz, CKP3, CKP2 and CKP1 must  
all be zero.  
0
Slow Arbitration  
Select  
SLOWARB  
This bit, when set, will divide the arbitration clock by 2. Memory  
cycle times will increase when slow arbitration is selected.  
NOTE: For clock multiplier output clock speeds greater than 40  
MHz, SLOWARB must be set. Defaults to low.  
Revision 12-05-06  
Page 36  
SMSC COM20020I Rev D  
DATASHEET  
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