5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Table 6.9 - Configuration Register
SYMBOL DESCRIPTION
BIT
BIT NAME
Reset
7
RESET
A software reset of the COM20020ID is executed by writing a logic
"1" to this bit. A software reset does not reset the microcontroller
interface mode, nor does it affect the Configuration Register. The
only registers that the software reset affect are the Status Register,
the Next ID Register, and the Diagnostic Status Register. This bit
must be brought back to logic "0" to release the reset.
6
5
Command
CCHEN
TXEN
This bit, if high, enables the Command Chaining operation of the
device. Please refer to the Command Chaining section for further
details. A low level on this bit ensures software compatibility with
previous SMSC ARCNET devices.
Chaining Enable
Transmit Enable
When low, this bit disables transmissions by keeping nPULSE1,
nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive.
When high, it enables the above signals to be activated during
transmissions. This bit defaults low upon reset. This bit is typically
enabled once the Node ID is determined, and never disabled during
normal operation. Please refer to the Improved Diagnostics section
for details on evaluating network activity.
4,3
Extended
ET1, ET2
These bits allow the network to operate over longer distances than
the default maximum 2 miles by controlling the Response, Idle, and
Reconfiguration Times. All nodes should be configured with the
same timeout values for proper network operation. For the
COM20020ID with a 20 MHz crystal oscillator, the bit combinations
follow:
Timeout 1,2
Reconfig
Response
Time (μS)
596.6
Idle Time
(μS)
656
Time (mS)
840
840
ET2
0
ET1
0
0
1
840
298.4
328
1
0
420
149.2
164
1
1
37.4
41
Note: These values are for 5Mbps and RCNTMR[1,0]=00.
Reconfiguration time is changed by the RCNTMR1 and
RCNTMR0 bits.
2
Backplane
BACK-
PLANE
A logic "1" on this bit puts the device into Backplane Mode signaling
which is used for Open Drain and Differential Driver interfaces.
1,0
Sub Address 1,0
SUBAD 1,0 These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD1
SUBAD0
Register
Tentative ID
Node ID
Setup 1
0
0
1
1
0
1
0
1
Next ID
See also the Sub Address Register.
SMSC COM20020I Rev D
Page 35
Revision 12-05-06
DATASHEET
SMSC [ SMSC CORPORATION ]
