ST7735
8.3 Serial interface characteristics (4-line serial)
Fig. 8.3.1 4-line serial interface timing
Signal
CSX
Symbol
TCSS
TCSH
TCSS
TSCC
TCHW
Parameter
MIN
15
15
60
65
40
66
30
30
150
60
60
MAX Unit Description
Chip select setup time (write)
Chip select hold time (write)
Chip select setup time (read)
Chip select hold time (read)
Chip select “H” pulse width
ns
ns
ns
ns
ns
ns
TSCYCW Serial clock cycle (Write)
-write command & data
TSHW
TSLW
SCL “H” pulse width (Write)
SCL “L” pulse width (Write)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ram
SCL
TSCYCR Serial clock cycle (Read)
-read command & data
ram
TSHR
TSLR
TDCS
TDCH
TSDS
TSDH
TACC
TOH
SCL “H” pulse width (Read)
SCL “L” pulse width (Read)
D/CX setup time
0
D/CX
D/CX hold time
10
10
10
10
Data setup time
SDA
Data hold time
For maximum CL=30pF
For minimum CL=8pF
(DIN)
Access time
50
50
(DOUT)
Output disable time
Table 8.3.1 4-line Serial Interface Characteristics
Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25
℃
Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%
and 70% of VDDI for Input signals.
V1.7
24
2009-12-04
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
