ST7565S
Table 25
Symbol
(VDD = 2.7 V , Ta = 25°C )
Rating
Item
Signal
Condition
Units
Min.
Max.
Address hold time
0
—
t
t
t
t
t
t
t
t
t
t
t
AH8
A0
Address setup time
0
—
—
AW8
System cycle time
400
220
180
220
180
40
CYC8
CCLW
CCHW
CCLR
CCHR
DS8
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
—
WR
RD
—
ns
—
—
—
15
—
DH8
D0 to D7
C
L
L
= 100 pF
= 100 pF
—
140
100
ACC8
OH8
READ Output disable time
C
10
Table 26
Symbol
(VDD = 1.8V , Ta = 25°C )
Rating
Item
Signal
Condition
Units
Min.
Max.
Address hold time
0
—
t
t
t
t
t
t
t
t
t
t
t
AH8
A0
Address setup time
0
—
—
—
—
—
AW8
System cycle time
640
360
280
360
280
80
CYC8
CCLW
CCHW
CCLR
CCHR
DS8
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
WR
RD
ns
—
—
30
DH8
D0 to D7
C
L
L
= 100 pF
= 100 pF
—
240
200
ACC8
OH8
READ Output disable time
C
10
*1 The input signal rise time and fall time (
) ≦ ( CCHW) for (
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 CCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level.
tr,
tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(
tr
+
tf
tCYC8
–
tCCLW
–
t
tr
+
tf
) ≦ ( CCHR) are specified.
t
CYC8 – tCCLR – t
tCCLW and t
Ver 0.6c
63/72
2009/09/07
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
