ST7565S
Table 32
Symbol
(VDD = 1.8V , Ta = 25°C )
Rating
Item
Serial Clock Period
Signal
Condition
Units
Min.
Max.
200
—
T
T
T
T
T
T
T
T
T
SCYC
SHW
SLW
SAS
SAH
SDS
SDH
CSS
CSH
SCL
SCL “H” pulse width
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
80
80
60
30
60
30
40
100
—
—
—
—
—
—
—
—
A0
SI
ns
CS-SCL time
CS
CS-SCL time
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 0.6c
67/72
2009/09/07