ST2202A
ꢀ
Base Timer Status Register
ꢀ
TABLE 12-5 Base Timer Status Register (BTSR)
Address Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Rꢀ
Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
BTSR[4]ꢀ BTSR[3]ꢀ BTSR[2]ꢀ BTSR[1]ꢀ BTSR[0]ꢀ 0ꢁꢀꢁ0ꢀ0000ꢀ
$021 BTSR
BTCLRꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
0ꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀ
ꢀ
ꢀ
Bitꢀ0:ꢀ ꢀ BTSR0 :ꢀ2ꢀHzꢀinterruptꢀstatusꢀbitꢀ
Bitꢀ3:ꢀ ꢀ BTSR3 :ꢀ256ꢀHzꢀinterruptꢀstatusꢀbitꢀ
0
ꢀ=ꢀNoꢀ2ꢀHzꢀinterruptꢀoccurred
0
ꢀ=ꢀNoꢀ256ꢀHzꢀinterruptꢀoccurred
1ꢀ=ꢀ2ꢀHzꢀinterruptꢀoccurredꢀ
ꢀ
1ꢀ=ꢀ256ꢀHzꢀinterruptꢀoccurredꢀ
ꢀ
Bitꢀ1:ꢀ ꢀ BTSR1 :ꢀ8ꢀHzꢀinterruptꢀstatusꢀbitꢀ
Bitꢀ4:ꢀ ꢀ BTSR4 :ꢀ2048ꢀHzꢀinterruptꢀstatusꢀbitꢀ
0
ꢀ=ꢀNoꢀ8ꢀHzꢀinterruptꢀoccurred
0
ꢀ=ꢀNoꢀ2048ꢀHzꢀinterruptꢀoccurred
1ꢀ=ꢀ8ꢀHzꢀinterruptꢀoccurredꢀ
1ꢀ=ꢀ2048ꢀHzꢀinterruptꢀoccurredꢀ
ꢀ
ꢀ
Bitꢀ2:ꢀ ꢀ BTSR2 :ꢀ64ꢀHzꢀinterruptꢀstatusꢀbitꢀ
Bitꢀ7:ꢀ ꢀ BTCLR :ꢀWriteꢀ“1”ꢀtoꢀclearꢀallꢀstatusꢀbitꢀ
0
ꢀ=ꢀNoꢀ64ꢀHzꢀinterruptꢀoccurred
1ꢀ=ꢀ64ꢀHzꢀinterruptꢀoccurredꢀ
Verꢀ2.5ꢀ
28
/
75
ꢀ
9/16/2008ꢀ