ST2202A
13. CLOCKING OUTPUTS
ThreeꢀclockingꢀoutputsꢀPE0,ꢀPE1ꢀandꢀPE2ꢀareꢀsupportedꢀbyꢀ
theꢀST2202.ꢀTheseꢀsignalsꢀareꢀveryꢀusefulꢀforꢀoutputsꢀofꢀhighꢀ
control.ꢀTimer0,ꢀTimer1ꢀoverflowꢀsignalsꢀareꢀclockꢀsourcesꢀforꢀ
PE0ꢀandꢀPE1,ꢀwhileꢀBGRCKꢀareꢀforꢀPE2.ꢀ ꢀ
frequency,ꢀsuchꢀasꢀPWMꢀbaseꢀsignalꢀorꢀcarrierꢀofꢀremoteꢀ
ꢀ
ꢀ
ꢀ
Clocking Outputs: PE0 and PE1
OverflowꢀstatesꢀofꢀTimersꢀwillꢀbeꢀconnectedꢀtoꢀtoggleꢀdataꢀofꢀ
PE[0:1]ꢀwhenꢀsettingꢀfunctionꢀselectionꢀbitsꢀTCO0/TCO1
PMCR[0:1]).ꢀMeanwhileꢀPE0/PE1ꢀoutputꢀclockedꢀdataꢀofꢀhalfꢀ
ꢀ
Clocking Output: PE2
BGRCKꢀwillꢀoutputꢀthroughꢀPE2ꢀwhenꢀsettingꢀfunctionꢀselectionꢀ
bitꢀBCOꢀ(PMCR[2]).ꢀIfꢀBCOꢀisꢀcleared,ꢀPE2ꢀreturnsꢀtoꢀtheꢀ
originalꢀlogicꢀlevelꢀofꢀPE[2].ꢀ
ꢀ
(
theꢀfrequencyꢀofꢀTimers.ꢀAfterꢀresettingꢀTCO0/TCO1,ꢀtheꢀtoggleꢀ
operationꢀceases.ꢀThenꢀPE0/PE1ꢀreturnꢀtoꢀtheꢀoriginalꢀlogicꢀ
levelꢀofꢀPE[0:1].ꢀ
ꢀ
SummaryꢀofꢀclockingꢀoutputsꢀregistersꢀisꢀshownꢀinꢀTABLEꢀ13ꢁ1.ꢀ
TheꢀclockingꢀoutputsꢀenableꢀbitsꢀcanꢀbeꢀfoundꢀinꢀTABLEꢀ13ꢁ2.ꢀ
ꢀ
TABLE 13-1 Summary Of Clocking Outputs Registers
Address Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
$004 PE
R/Wꢀ PE[7]ꢀ
PE[6]ꢀ
PE[5]ꢀ
PE[4]ꢀ
PE[3]ꢀ
PE[2]ꢀ
PE[1]ꢀ
PE[0]ꢀ
1111ꢀ1111ꢀ
$00C PCE
$00F PMCR
R/Wꢀ PCE[7]ꢀ PCE[6]ꢀ PCE[5]ꢀ PCE[4]ꢀ PCE[3]ꢀ PCE[2]ꢀ PCE[1]ꢀ PCE[0]ꢀ 0000ꢀ0000ꢀ
R/Wꢀ PULLꢀ
PDBNꢀ INTEGꢀ CSM1ꢀ CSM0ꢀ
BCOꢀ
TCO1ꢀ
TCO0ꢀ
1000ꢀꢁ000ꢀ
ꢀ
TABLE 13-2 Port Miscellaneous Control Register (PMCR)
Address Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
$00F PMCR
R/Wꢀ
PULLꢀ
PDBNꢀ INTEGꢀ CSM1ꢀ CSM0ꢀ
BCOꢀ
TCO1ꢀ
TCO0ꢀ
1000ꢀ0000ꢀ
ꢀ
Bitꢀ0:ꢀ ꢀ TCO0 :ꢀClockingꢀoutputꢀPE0ꢀcontrolꢀbitꢀ(sourcedꢀfromꢀTimer0)ꢀ
ꢀ=ꢀDisableꢀclockingꢀoutputꢀofꢀPE0
0
1ꢀ=ꢀEnableꢀclockingꢀoutputꢀofꢀPE0ꢀ
ꢀ
Bitꢀ1:ꢀ ꢀ TCO1 :ꢀClockingꢀoutputꢀPE1ꢀcontrolꢀbitꢀ(sourcedꢀfromꢀTimer1)ꢀ
0
ꢀ=ꢀDisableꢀclockingꢀoutputꢀofꢀPE1
1ꢀ=ꢀEnableꢀclockingꢀoutputꢀofꢀPE1ꢀ
ꢀ
Bitꢀ2:ꢀ ꢀ BCO :ꢀClockꢀsignalꢀoutputꢀPE2ꢀcontrolꢀbitꢀ(sourcedꢀfromꢀBGRCK)ꢀ
0
ꢀ=ꢀDisableꢀclockꢀsignalꢀoutputꢀofꢀPE2
1ꢀ=ꢀEnableꢀclockꢀsignalꢀoutputꢀofꢀPE2ꢀ
ꢀ
Verꢀ2.5ꢀ
31
/75
ꢀ
9/16/2008ꢀ
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