ST2202A
12.4 Timer 1
TheꢀTimer1ꢀisꢀanꢀ8ꢁbitꢀupꢀcounter.ꢀItꢀusedꢀasꢀtimer/counterꢀasꢀprogramꢀspecified.ꢀTheꢀdifferenceꢀbetweenꢀbaseꢀtimerꢀisꢀthatꢀTimer1ꢀ
willꢀhaltꢀduringꢀCPUꢀSBY,ꢀbutꢀbaseꢀtimerꢀwillꢀnot.ꢀItꢀisꢀshownꢀinꢀFIGUREꢀ12ꢁ4.ꢀ
MUXꢀ8ꢁ1
TCLK/65536
IN0
TCLK/32768
IN1
TCLK/8192
IN2
TCLK/2048
IN3
PRES
OUT
TCLK/256
IN4
MUX
MUX
DꢀFlipꢁFlop
CK
TCLK/32
TCLK/8
TCLK/2
IN5
IN6
IN7
OUT
D
Q
IN0
IN1
SYSCK
SEL
SEL
T1M[2~0]
T1M[3]
MUX4ꢁ1
OSCX/256
OSCX/128
OSCX/64
BGRCK
IN0
IN1
IN2
IN3
8ꢀBitꢀꢁꢀUPꢀCounter
CLOCK
IRT1
PREW
OUT
T1M[4]
AutoꢀReload
SEL
T1M[1~0]
ꢀ
FIGURE 12-4 Timer1 Structure
ꢀ
ꢀ
TABLE 12-8 Timer1 Register (T1C)
Address Name R/W
$027 T1C
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
R/Wꢀ
T1C[7]ꢀ T1C[6]ꢀ T1C[5]ꢀ T1C[4]ꢀ T1C[3]ꢀ T1C[2]ꢀ T1C[1]ꢀ T1C[0]ꢀ 0000ꢀ0000ꢀ
ꢀ
Bitꢀ7ꢁ0:ꢀ ꢀ ꢀ ꢀ ꢀ T1C[7-0] :ꢀTimer1ꢀupꢀcounterꢀregisterꢀ
ꢀ
TABLE 12-9 Clock Sources Of Timer1
T1M[3] T1M[2]
T1M[1] T1M[0]
T1ꢀTimerꢀClockꢀSource
TCLK/65536
TCLK/32768
TCLK/8192
TCLK/2048
TCLK/256
TCLK/32
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
TCLK/8
TCLK/2
OSCX/256
OSCX/128
OSCX/64
BGRCK
ꢀ
ꢀ
T1M[4]:ꢀControlꢀautomaticꢀreloadꢀoperationꢀ
ꢀ
ꢀ
0:ꢀNoꢀautoꢀreloadꢀ
1:ꢀautoꢀreloadꢀ
SENAꢀ:ꢀPrescalerꢀenableꢀbitꢀ
ꢀ
ꢀ
0ꢀ:ꢀTCLKꢀstopꢀ
1ꢀ:ꢀTCLKꢀcountingꢀ
Verꢀ2.5ꢀ
30
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
