STK10C68
SRAM READ CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
STK10C68-25 STK10C68-35 STK10C68-45 STK10C68-55
PARAMETER
UNITS
NO.
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
25
35
45
55
AVAV
RC
AA
g
3
Address Access Time
25
10
35
15
45
20
55
25
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
g
5
5
5
5
5
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
10
10
35
12
12
45
12
12
55
EHQZ
HZ
8
0
0
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
EHICCL
d, e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note g: I/O state assumes E, G < VIL, W > VIH , and NE ≥ VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
f, g
SRAM READ CYCLE #1: Address Controlled
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
f
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
1
11
EHICCL
t
ELQV
t
6
ELQX
E
t
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DATA VALID
DQ (DATA OUT)
10
ELICCH
t
ACTIVE
STANDBY
I
CC
March 2006
3
Document Control # ML0006 rev 0.2
SIMTEK [ SIMTEK CORPORATION ]
