STK10C68
DEVICE OPERATION
The STK10C68 has two modes of operation: SRAM
mode and nonvolatile mode, determined by the
state of the NE pin. When in SRAM mode, the mem-
ory operates as a standard fast static RAM. While in
nonvolatile mode, data is transferred in parallel from
SRAM to Nonvolatile Elements or from Nonvolatile
Elements to SRAM.
NONVOLATILE STORE
A STORE cycle is performed when NE, E and W and
low and G is high. While any sequence that
achieves this state will initiate a STORE, only W initi-
ation (STORE cycle #1) and E initiation (STORE cycle
#2) are practical without risking an unintentional
SRAM WRITE that would disturb SRAM data. During a
STORE cycle, previous nonvolatile data is erased
and the SRAM contents are then programmed into
nonvolatile elements. Once a STORE cycle is initi-
ated, further input and output are disabled and the
DQ0-7 pins are tri-stated until the cycle is complete.
NOISE CONSIDERATIONS
Note that the STK10C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
If E and G are low and W and NE are high at the end
of the cycle, a READ will be performed and the out-
puts will go active, signaling the end of the STORE.
NONVOLATILE RECALL
SRAM READ
A RECALL cycle is performed when E, G and NE are
low and W is high. Like the STORE cycle, RECALL is
initiated when the last of the four clock signals goes
to the RECALL state. Once initiated, the RECALL
cycle will take tNLQX to complete, during which all
inputs are ignored. When the RECALL completes,
any READ or WRITE state on the input pins will take
effect.
The STK10C68 performs a READ cycle whenever E
and G are low and NE and W are high. The address
specified on pins A0-12 determines which of the 8,192
data bytes will be accessed. When the READ is initi-
ated by an address transition, the outputs will be
valid after a delay of tAVQV (READ cycle #1). If the
READ is initiated by E or G, the outputs will be valid
at tELQV or at tGLQV, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address
changes within the tAVQV access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high or W or NE is brought low.
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
nonvolatile cells. The nonvolatile data can be
recalled an unlimited number of times.
SRAM WRITE
As with the STORE cycle, a transition must occur on
any one control pin to cause a RECALL, preventing
inadvertent multi-triggering. On power up, once VCC
exceeds the VCC sense voltage of 4.25V, a RECALL
cycle is automatically initiated. Due to this automatic
RECALL, SRAM operation cannot commence until
A WRITE cycle is performed whenever E and W are
low and NE is high. The address inputs must be sta-
ble prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
tRESTORE after VCC exceeds approximately 4.25V.
POWER-UP RECALL
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
During power up, or after any low-power condition
(VCC < 3.0V), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of 4.25V, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
March 2006
8
Document Control # ML0006 rev 0.2
SIMTEK [ SIMTEK CORPORATION ]
