SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Internal Register Space – Base Address 4
Access to these registers is modified by the “shadow” Device Select bits.
These registers are 32-bits wide and define the internal operation of the SiI3114. The access types are defined as
follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O
space. Table 21 shows the internal register space for base 4 addresses.
Table 21. SiI3114 Internal Register Space – Base Address 4
Address
Offset
Register Name
16 15
PCI Bus Master
Access
Type
31
00
PCI Bus Master
Command –
Channel 0/2
Status –
00H
04H
08H
0CH
Reserved
Reserved
Software Data
R/W
R/W
R/W
R/W
Channel 0/2
PRD Table Address – Channel 0/2
PCI Bus Master
PCI Bus Master
Command –
Channel 1/3
Status –
Reserved
Channel 1/3
PRD Table Address – Channel 1/3
PCI Bus Master – Channel 0/2
Address Offset: 00H
Access Type: Read/Write
Reset Value: 0x0000_XX00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Software
Reserved
This register defines the PCI bus master register for Channel 0/2 in the SiI3114. See “PCI Bus Master – Channel
X” section on page 53 for bit definitions. The value in the “shadow” Channel 0/2 Device Select bit is used to
control access to the appropriate Channel 0 (Master; bit is 0) or Channel 2 (Slave; bit is 1) PCI Bus Master
register bits. (The “shadow” Channel 1/3 Device Select bit controls the Channel 1/3 DMA Comp bit.)
PRD Table Address – Channel 0/2
Address Offset: 04H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – Channel 0/2
This register defines the PRD Table Address register for Channel 0/2 in the SiI3114. The register bits are also
mapped to PCI Configuration Space, Offset 74H and Base Address 5, Offset 04H. See “PRD Table Address –
Channel X” section on page 54 for bit definitions. Writing to this register address results in both the Channel 0 and
Channel 2 PRD Table Address registers being written. The read value is selected based upon the “shadow”
Channel 0/2 Device Select bit.
SiI-DS-0103-D
44
© 2007 Silicon Image, Inc.
SILICONIMAGE [ Silicon image ]
