SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
written to bit 4 of either Device+Head Task File register while the value being written to bit 4 is written to the
“shadow” Device Select bit.
Internal Register Space – Base Address 3
Access to this register is modified by the “shadow” Channel 1/3 Device Select bit.
These registers are 32-bits wide and define the internal operation of the SiI3114. The access types are defined as
follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O
space. Table 20 shows the internal register space for base 3 addresses.
Table 20. SiI3114 Internal Register Space – Base Address 3
Address
Offset
Register Name
16 15
Device Control
Auxiliary Status
Access
Type
31
00
00H
Reserved
Reserved
Reserved
R/W
Channel 1/3 Task File Register 2
Address Offset: 00H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device Control
Auxiliary Status
Reserved
Reserved
Reserved
This register defines one of the Channel 1/3 Task File registers in the SiI3114. The register bits are also mapped
to Base Address 5, Offset C8H. See “Channel X Task File Register 2” section on page 63 for bit definitions. The
value in the “shadow” Channel 1/3 Device Select bit is used to select the Task File registers for either Channel 1
(Master; bit is 0) or Channel 3 (Slave; bit is 1).
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
