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SII3114CTU 参数 Datasheet PDF下载

SII3114CTU图片预览
型号: SII3114CTU
PDF下载: 下载PDF文件 查看货源
内容描述: PCI串行ATA控制器 [PCI to Serial ATA Controller]
分类和应用: 外围集成电路控制器PC时钟
文件页数/大小: 127 页 / 559 K
品牌: SILICONIMAGE [ Silicon image ]
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SiI3114 PCI to Serial ATA Controller  
Data Sheet  
Silicon Image, Inc.  
Internal Register Space – Base Address 5  
These registers are 32-bits wide and define the internal operation of the SiI3114. The access types are defined as  
follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI  
Memory space. Base Address 5 accesses can be disabled by setting input BA5_EN low. Table 22 shows the  
internal register space for base 5 addresses.  
Table 22. SiI3114 Internal Register Space – Base Address 5  
Address  
Offset  
Register Name  
16 15  
PCI Bus Master  
Access  
Type  
31  
00  
PCI Bus Master  
R/W  
00H  
04H  
08H  
0CH  
10H  
14H  
18H  
Reserved  
Reserved  
Status – Channel  
0
Software Data  
Command –  
Channel 0  
PRD Table Address – Channel 0  
PCI Bus Master  
Status – Channel  
1
R/W  
R/W  
PCI Bus Master  
Command –  
Channel 1  
Reserved  
PRD Table Address – Channel 1  
PCI Bus Master  
Status2 – Channel  
0
R/W  
R/W  
PCI Bus Master  
Status – Channel  
1
PCI Bus Master  
Command2 –  
Channel 0  
Software Data  
Reserved  
Reserved  
-
PCI Bus Master  
Status2 – Channel  
1
PCI Bus Master  
Command2 –  
Channel 1  
R/W  
Reserved  
1CH  
20H  
24H  
28H  
2CH  
30H  
34H  
38H  
3CH  
Reserved  
-
PRD Address – Channel 0  
PCI Bus Master Byte Count – Channel 0  
PRD Address – Channel 1  
PCI Bus Master Byte Count – Channel 1  
Reserved  
R
R
R
R
-
Reserved  
-
Reserved  
-
-
Reserved  
FIFO Wr Request  
FIFO Rd Request  
R/W  
40H  
44H  
FIFO Valid Byte Count – Channel 0  
Control – Channel Control – Channel  
0
0
FIFO Wr Request  
FIFO Rd Request  
R/W  
FIFO Valid Byte Count – Channel 1  
System Configuration Status  
Control – Channel Control – Channel  
1
1
48H  
4CH  
50H  
System Command  
R/W  
R/W  
R/W  
R/W  
System Software Data  
Flash Memory Address – Command and Status  
Flash Memory  
Data  
54H  
58H  
5CH  
Reserved  
EEPROM Memory Address – Command and Status  
EEPROM Memory  
GPIO Control  
R/W  
R/W  
Reserved  
FIFO Port – Channel 0  
Reserved  
Data  
60H  
64H  
R/W  
-
FIFO Byte1 Write  
Pointer – Channel  
0
FIFO Byte1 Read  
Pointer – Channel  
0
FIFO Byte0 Write  
Pointer – Channel  
0
FIFO Byte0 Read  
Pointer – Channel  
0
R
68H  
SiI-DS-0103-D  
46  
© 2007 Silicon Image, Inc.  
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