SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
PCI Bus Master – Channel 1/3
Address Offset: 08H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Reserved
This register defines the PCI bus master register for Channel 1/3 in the SiI3114. See “PRD Table Address –
Channel X” section on page 54 for bit definitions. The value in the “shadow” Channel 1/3 Device Select bit is used
to control access to the appropriate Channel 1 (Master; bit is 0) or Channel 3 (Slave; bit is 1) PCI Bus Master
register bits.
PRD Table Address – Channel 1/3
Address Offset: 0CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – Channel 1/3
This register defines the PRD Table Address register for Channel 1/3 in the SiI3114. The register bits are also
mapped to PCI Configuration Space, Offset 7CH and Base Address 5, Offset 0CH. See “PRD Table Address –
Channel X” section on page 54 for bit definitions. Writing to this register address results in both the Channel 1 and
Channel 3 PRD Table Address registers being written. The read value is selected based upon the “shadow”
Channel 1/3 Device Select bit.
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
