SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Internal Register Space – Base Address 0
Access to these registers is modified by the “shadow” Channel 0/2 Device Select bit. The “shadow” Channel 0/2
Device Select bit is written from bit 4 of the byte written to the Channel 0/2 Task File Device+Head register (06H).
These registers are 32-bits wide and define the internal operation of the SiI3114. The access types are defined as
follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O
space. Table 17 shows the internal register space for base 0 addresses.
Table 17. SiI3114 Internal Register Space – Base Address 0
Address
Offset
Register Name
16 15
Sector Count Features (W)
Access
Type
31
Starting Sector
00
00H
04H
Data
R/W
R/W
Number
Error (R)
Command+Status
Device+Head
Cylinder High
Cylinder Low
Channel 0/2 Task File Register 0
Address Offset: 00H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Starting Sector Number
Sector Count
Features (W) Error (R)
Data (byte access)
Data (word access)
Data (dword access)
This register defines four of the Channel 0/2 Task File registers in the SiI3114. The register bits are also mapped
to Base Address 5, Offset 80H. See “Channel X Task File Register 0” section on page 62 for bit definitions. The
value in the “shadow” Channel 0/2 Device Select bit is used to select the Task File registers for either Channel 0
(Master, bit is 0) or Channel 2 (Slave, bit is 1).
Channel 0/2 Task File Register 1
Address Offset: 04H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Command + Status
Device+Head
Cylinder High
Cylinder Low
This register defines four of the Channel 0/2 Task File registers in the SiI3114. The register bits are also mapped
to Base Address 5, Offset 84H. See “Channel X Task File Register 1” section on page 62 for bit definitions. Except
for writing the Device+Head Task File register, the value in the “shadow” Channel 0/2 Device Select bit is used to
select the Task File registers for either Channel 0 (Master; bit is 0) or Channel 2 (Slave; bit is 1). For writing the
Device+Head Task File register, the value being written to bit 4 of the register (the Device Select bit) is used to
select the Task File register for either Channel 0 (Master; bit is 0) or Channel 2 (Slave; bit is 1); a 0 is always
written to bit 4 of either Device+Head Task File register while the value being written to bit 4 is written to the
“shadow” Device Select bit.
SiI-DS-0103-D
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© 2007 Silicon Image, Inc.
SILICONIMAGE [ Silicon image ]
